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/**************************************************************************
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slichw.h
*
* This header file contains definitions that are common to our hardware.
*/
#ifndef __SLICHW_H__
#define __SLICHW_H__
#define PCI_VENDOR_ID_ALACRITECH 0x139A
#define SLIC_1GB_DEVICE_ID 0x0005
#define SLIC_2GB_DEVICE_ID 0x0007 /* Oasis Device ID */
#define SLIC_1GB_CICADA_SUBSYS_ID 0x0008
#define SLIC_NBR_MACS 4
#define SLIC_RCVBUF_SIZE 2048
#define SLIC_RCVBUF_HEADSIZE 34
#define SLIC_RCVBUF_TAILSIZE 0
#define SLIC_RCVBUF_DATASIZE (SLIC_RCVBUF_SIZE - \
(SLIC_RCVBUF_HEADSIZE + \
SLIC_RCVBUF_TAILSIZE))
#define VGBSTAT_XPERR 0x40000000
#define VGBSTAT_XERRSHFT 25
#define VGBSTAT_XCSERR 0x23
#define VGBSTAT_XUFLOW 0x22
#define VGBSTAT_XHLEN 0x20
#define VGBSTAT_NETERR 0x01000000
#define VGBSTAT_NERRSHFT 16
#define VGBSTAT_NERRMSK 0x1ff
#define VGBSTAT_NCSERR 0x103
#define VGBSTAT_NUFLOW 0x102
#define VGBSTAT_NHLEN 0x100
#define VGBSTAT_LNKERR 0x00000080
#define VGBSTAT_LERRMSK 0xff
#define VGBSTAT_LDEARLY 0x86
#define VGBSTAT_LBOFLO 0x85
#define VGBSTAT_LCODERR 0x84
#define VGBSTAT_LDBLNBL 0x83
#define VGBSTAT_LCRCERR 0x82
#define VGBSTAT_LOFLO 0x81
#define VGBSTAT_LUFLO 0x80
#define IRHDDR_FLEN_MSK 0x0000ffff
#define IRHDDR_SVALID 0x80000000
#define IRHDDR_ERR 0x10000000
#define VRHSTAT_802OE 0x80000000
#define VRHSTAT_TPOFLO 0x10000000
#define VRHSTATB_802UE 0x80000000
#define VRHSTATB_RCVE 0x40000000
#define VRHSTATB_BUFF 0x20000000
#define VRHSTATB_CARRE 0x08000000
#define VRHSTATB_LONGE 0x02000000
#define VRHSTATB_PREA 0x01000000
#define VRHSTATB_CRC 0x00800000
#define VRHSTATB_DRBL 0x00400000
#define VRHSTATB_CODE 0x00200000
#define VRHSTATB_TPCSUM 0x00100000
#define VRHSTATB_TPHLEN 0x00080000
#define VRHSTATB_IPCSUM 0x00040000
#define VRHSTATB_IPLERR 0x00020000
#define VRHSTATB_IPHERR 0x00010000
#define SLIC_MAX64_BCNT 23
#define SLIC_MAX32_BCNT 26
#define IHCMD_XMT_REQ 0x01
#define IHFLG_IFSHFT 2
#define SLIC_RSPBUF_SIZE 32
#define SLIC_RESET_MAGIC 0xDEAD
#define ICR_INT_OFF 0
#define ICR_INT_ON 1
#define ICR_INT_MASK 2
#define ISR_ERR 0x80000000
#define ISR_RCV 0x40000000
#define ISR_CMD 0x20000000
#define ISR_IO 0x60000000
#define ISR_UPC 0x10000000
#define ISR_LEVENT 0x08000000
#define ISR_RMISS 0x02000000
#define ISR_UPCERR 0x01000000
#define ISR_XDROP 0x00800000
#define ISR_UPCBSY 0x00020000
#define ISR_EVMSK 0xffff0000
#define ISR_PINGMASK 0x00700000
#define ISR_PINGDSMASK 0x00710000
#define ISR_UPCMASK 0x11000000
#define SLIC_WCS_START 0x80000000
#define SLIC_WCS_COMPARE 0x40000000
#define SLIC_RCVWCS_BEGIN 0x40000000
#define SLIC_RCVWCS_FINISH 0x80000000
#define SLIC_PM_MAXPATTERNS 6
#define SLIC_PM_PATTERNSIZE 128
#define SLIC_PMCAPS_WAKEONLAN 0x00000001
#define MIICR_REG_PCR 0x00000000
#define MIICR_REG_4 0x00040000
#define MIICR_REG_9 0x00090000
#define MIICR_REG_16 0x00100000
#define PCR_RESET 0x8000
#define PCR_POWERDOWN 0x0800
#define PCR_SPEED_100 0x2000
#define PCR_SPEED_1000 0x0040
#define PCR_AUTONEG 0x1000
#define PCR_AUTONEG_RST 0x0200
#define PCR_DUPLEX_FULL 0x0100
#define PSR_LINKUP 0x0004
#define PAR_ADV100FD 0x0100
#define PAR_ADV100HD 0x0080
#define PAR_ADV10FD 0x0040
#define PAR_ADV10HD 0x0020
#define PAR_ASYMPAUSE 0x0C00
#define PAR_802_3 0x0001
#define PAR_ADV1000XFD 0x0020
#define PAR_ADV1000XHD 0x0040
#define PAR_ASYMPAUSE_FIBER 0x0180
#define PGC_ADV1000FD 0x0200
#define PGC_ADV1000HD 0x0100
#define SEEQ_LINKFAIL 0x4000
#define SEEQ_SPEED 0x0080
#define SEEQ_DUPLEX 0x0040
#define TDK_DUPLEX 0x0800
#define TDK_SPEED 0x0400
#define MRV_REG16_XOVERON 0x0068
#define MRV_REG16_XOVEROFF 0x0008
#define MRV_SPEED_1000 0x8000
#define MRV_SPEED_100 0x4000
#define MRV_SPEED_10 0x0000
#define MRV_FULLDUPLEX 0x2000
#define MRV_LINKUP 0x0400
#define GIG_LINKUP 0x0001
#define GIG_FULLDUPLEX 0x0002
#define GIG_SPEED_MASK 0x000C
#define GIG_SPEED_1000 0x0008
#define GIG_SPEED_100 0x0004
#define GIG_SPEED_10 0x0000
#define MCR_RESET 0x80000000
#define MCR_CRCEN 0x40000000
#define MCR_FULLD 0x10000000
#define MCR_PAD 0x02000000
#define MCR_RETRYLATE 0x01000000
#define MCR_BOL_SHIFT 21
#define MCR_IPG1_SHIFT 14
#define MCR_IPG2_SHIFT 7
#define MCR_IPG3_SHIFT 0
#define GMCR_RESET 0x80000000
#define GMCR_GBIT 0x20000000
#define GMCR_FULLD 0x10000000
#define GMCR_GAPBB_SHIFT 14
#define GMCR_GAPR1_SHIFT 7
#define GMCR_GAPR2_SHIFT 0
#define GMCR_GAPBB_1000 0x60
#define GMCR_GAPR1_1000 0x2C
#define GMCR_GAPR2_1000 0x40
#define GMCR_GAPBB_100 0x70
#define GMCR_GAPR1_100 0x2C
#define GMCR_GAPR2_100 0x40
#define XCR_RESET 0x80000000
#define XCR_XMTEN 0x40000000
#define XCR_PAUSEEN 0x20000000
#define XCR_LOADRNG 0x10000000
#define RCR_RESET 0x80000000
#define RCR_RCVEN 0x40000000
#define RCR_RCVALL 0x20000000
#define RCR_RCVBAD 0x10000000
#define RCR_CTLEN 0x08000000
#define RCR_ADDRAEN 0x02000000
#define GXCR_RESET 0x80000000
#define GXCR_XMTEN 0x40000000
#define GXCR_PAUSEEN 0x20000000
#define GRCR_RESET 0x80000000
#define GRCR_RCVEN 0x40000000
#define GRCR_RCVALL 0x20000000
#define GRCR_RCVBAD 0x10000000
#define GRCR_CTLEN 0x08000000
#define GRCR_ADDRAEN 0x02000000
#define GRCR_HASHSIZE_SHIFT 17
#define GRCR_HASHSIZE 14
#define SLIC_EEPROM_ID 0xA5A5
#define SLIC_SRAM_SIZE2GB (64 * 1024)
#define SLIC_SRAM_SIZE1GB (32 * 1024)
#define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */
#define SLIC_NBR_MACS 4
struct slic_rcvbuf {
u8 pad1[6];
u16 pad2;
u32 pad3;
u32 pad4;
u32 buffer;
u32 length;
u32 status;
u32 pad5;
u16 pad6;
u8 data[SLIC_RCVBUF_DATASIZE];
};
struct slic_hddr_wds {
union {
struct {
u32 frame_status;
u32 frame_status_b;
u32 time_stamp;
u32 checksum;
} hdrs_14port;
struct {
u32 frame_status;
u16 ByteCnt;
u16 TpChksum;
u16 CtxHash;
u16 MacHash;
u32 BufLnk;
} hdrs_gbit;
} u0;
};
#define frame_status14 u0.hdrs_14port.frame_status
#define frame_status_b14 u0.hdrs_14port.frame_status_b
#define frame_statusGB u0.hdrs_gbit.frame_status
struct slic_host64sg {
u32 paddrl;
u32 paddrh;
u32 length;
};
struct slic_host64_cmd {
u32 hosthandle;
u32 RSVD;
u8 command;
u8 flags;
union {
u16 rsv1;
u16 rsv2;
} u0;
union {
struct {
u32 totlen;
struct slic_host64sg bufs[SLIC_MAX64_BCNT];
} slic_buffers;
} u;
};
struct slic_rspbuf {
u32 hosthandle;
u32 pad0;
u32 pad1;
u32 status;
u32 pad2[4];
};
struct slic_regs {
u32 slic_reset; /* Reset Register */
u32 pad0;
u32 slic_icr; /* Interrupt Control Register */
u32 pad2;
#define SLIC_ICR 0x0008
u32 slic_isp; /* Interrupt status pointer */
u32 pad1;
#define SLIC_ISP 0x0010
u32 slic_isr; /* Interrupt status */
u32 pad3;
#define SLIC_ISR 0x0018
u32 slic_hbar; /* Header buffer address reg */
u32 pad4;
/*
* 31-8 - phy addr of set of contiguous hdr buffers
* 7-0 - number of buffers passed
* Buffers are 256 bytes long on 256-byte boundaries.
*/
#define SLIC_HBAR 0x0020
#define SLIC_HBAR_CNT_MSK 0x000000FF
u32 slic_dbar; /* Data buffer handle & address reg */
u32 pad5;
/* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
#define SLIC_DBAR 0x0028
#define SLIC_DBAR_SIZE 2048
u32 slic_cbar; /* Xmt Cmd buf addr regs.*/
/*
* 1 per XMT interface
* 31-5 - phy addr of host command buffer
* 4-0 - length of cmd in multiples of 32 bytes
* Buffers are 32 bytes up to 512 bytes long
*/
#define SLIC_CBAR 0x0030
#define SLIC_CBAR_LEN_MSK 0x0000001F
#define SLIC_CBAR_ALIGN 0x00000020
u32 slic_wcs; /* write control store*/
#define SLIC_WCS 0x0034
#define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/
#define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/
u32 slic_rbar; /* Response buffer address reg.*/
u32 pad7;
/*
* 31-8 - phy addr of set of contiguous response buffers
* 7-0 - number of buffers passed
* Buffers are 32 bytes long on 32-byte boundaries.
*/
#define SLIC_RBAR 0x0038
#define SLIC_RBAR_CNT_MSK 0x000000FF
#define SLIC_RBAR_SIZE 32
u32 slic_stats; /* read statistics (UPR) */
u32 pad8;
#define SLIC_RSTAT 0x0040
u32 slic_rlsr; /* read link status */
u32 pad9;
#define SLIC_LSTAT 0x0048
u32 slic_wmcfg; /* Write Mac Config */
u32 pad10;
#define SLIC_WMCFG 0x0050
u32 slic_wphy; /* Write phy register */
u32 pad11;
#define SLIC_WPHY 0x0058
u32 slic_rcbar; /* Rcv Cmd buf addr reg */
u32 pad12;
#define SLIC_RCBAR 0x0060
u32 slic_rconfig; /* Read SLIC Config*/
u32 pad13;
#define SLIC_RCONFIG 0x0068
u32 slic_intagg; /* Interrupt aggregation time */
u32 pad14;
#define SLIC_INTAGG 0x0070
u32 slic_wxcfg; /* Write XMIT config reg*/
u32 pad16;
#define SLIC_WXCFG 0x0078
u32 slic_wrcfg; /* Write RCV config reg*/
u32 pad17;
#define SLIC_WRCFG 0x0080
u32 slic_wraddral; /* Write rcv addr a low*/
u32 pad18;
#define SLIC_WRADDRAL 0x0088
u32<
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