path: root/drivers/staging/rts5208/rtsx_chip.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Driver for Realtek PCI-Express card reader
 *
 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
 *
 * Author:
 *   Wei WANG (wei_wang@realsil.com.cn)
 *   Micky Ching (micky_ching@realsil.com.cn)
 */

#ifndef __REALTEK_RTSX_CHIP_H
#define __REALTEK_RTSX_CHIP_H

#include "rtsx.h"

#define SUPPORT_CPRM
#define SUPPORT_OCP
#define SUPPORT_SDIO_ASPM
#define SUPPORT_MAGIC_GATE
#define SUPPORT_MSXC
#define SUPPORT_SD_LOCK
/* Hardware switch bus_ctl and cd_ctl automatically */
#define HW_AUTO_SWITCH_SD_BUS
/* Enable hardware interrupt write clear */
#define HW_INT_WRITE_CLR
/* #define LED_AUTO_BLINK */
/* #define DISABLE_CARD_INT */

#ifdef SUPPORT_MAGIC_GATE
	/* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */
	#define MG_SET_ICV_SLOW
	/* HW may miss ERR/CMDNK signal when sampling INT status. */
	#define MS_SAMPLE_INT_ERR
	/*
	 * HW DO NOT support Wait_INT function
	 * during READ_BYTES transfer mode
	 */
	#define READ_BYTES_WAIT_INT
#endif

#ifdef SUPPORT_MSXC
#define XC_POWERCLASS
#define SUPPORT_PCGL_1P18
#endif

#ifndef LED_AUTO_BLINK
#define REGULAR_BLINK
#endif

#define LED_BLINK_SPEED		5
#define LED_TOGGLE_INTERVAL	6
#define	GPIO_TOGGLE_THRESHOLD   1024
#define LED_GPIO		0

#define POLLING_INTERVAL	30

#define TRACE_ITEM_CNT		64

#ifndef STATUS_SUCCESS
#define STATUS_SUCCESS		0
#endif
#ifndef STATUS_FAIL
#define STATUS_FAIL		1
#endif
#ifndef STATUS_TIMEDOUT
#define STATUS_TIMEDOUT		2
#endif
#ifndef STATUS_NOMEM
#define STATUS_NOMEM		3
#endif
#ifndef STATUS_READ_FAIL
#define STATUS_READ_FAIL	4
#endif
#ifndef STATUS_WRITE_FAIL
#define STATUS_WRITE_FAIL	5
#endif
#ifndef STATUS_ERROR
#define STATUS_ERROR		10
#endif

#define PM_S1			1
#define PM_S3			3

/*
 * Transport return codes
 */

#define TRANSPORT_GOOD		0   /* Transport good, command good	   */
#define TRANSPORT_FAILED	1   /* Transport good, command failed   */
#define TRANSPORT_NO_SENSE	2  /* Command failed, no auto-sense    */
#define TRANSPORT_ERROR		3   /* Transport bad (i.e. device dead) */

/*
 * Start-Stop-Unit
 */
#define STOP_MEDIUM			0x00    /* access disable         */
#define MAKE_MEDIUM_READY		0x01    /* access enable          */
#define UNLOAD_MEDIUM			0x02    /* unload                 */
#define LOAD_MEDIUM			0x03    /* load                   */

/*
 * STANDARD_INQUIRY
 */
#define QULIFIRE                0x00
#define AENC_FNC                0x00
#define TRML_IOP                0x00
#define REL_ADR                 0x00
#define WBUS_32                 0x00
#define WBUS_16                 0x00
#define SYNC                    0x00
#define LINKED                  0x00
#define CMD_QUE                 0x00
#define SFT_RE                  0x00

#define VEN_ID_LEN              8               /* Vendor ID Length         */
#define PRDCT_ID_LEN            16              /* Product ID Length        */
#define PRDCT_REV_LEN           4               /* Product LOT Length       */

/* Dynamic flag definitions: used in set_bit() etc. */
/* 0x00040000 transfer is active */
#define RTSX_FLIDX_TRANS_ACTIVE		18
/* 0x00100000 abort is in progress */
#define RTSX_FLIDX_ABORTING		20
/* 0x00200000 disconnect in progress */
#define RTSX_FLIDX_DISCONNECTING	21

#define ABORTING_OR_DISCONNECTING	((1UL << US_FLIDX_ABORTING) | \
					 (1UL << US_FLIDX_DISCONNECTING))

/* 0x00400000 device reset in progress */
#define RTSX_FLIDX_RESETTING		22
/* 0x00800000 SCSI midlayer timed out  */
#define RTSX_FLIDX_TIMED_OUT		23
#define DRCT_ACCESS_DEV         0x00    /* Direct Access Device      */
#define RMB_DISC                0x80    /* The Device is Removable   */
#define ANSI_SCSI2              0x02    /* Based on ANSI-SCSI2       */

#define SCSI                    0x00    /* Interface ID              */

#define	WRITE_PROTECTED_MEDIA 0x07

/*---- sense key ----*/
#define ILI                     0x20    /* ILI bit is on                    */

#define NO_SENSE                0x00    /* not exist sense key              */
#define RECOVER_ERR             0x01    /* Target/Logical unit is recoverd  */
#define NOT_READY               0x02    /* Logical unit is not ready        */
#define MEDIA_ERR               0x03    /* medium/data error                */
#define HARDWARE_ERR            0x04    /* hardware error                   */
#define ILGAL_REQ               0x05    /* CDB/parameter/identify msg error */
#define UNIT_ATTENTION          0x06    /* unit attention condition occur   */
#define DAT_PRTCT               0x07    /* read/write is desable            */
#define BLNC_CHK                0x08    /* find blank/DOF in read           */
					/* write to unblank area            */
#define CPY_ABRT                0x0a    /* Copy/Compare/Copy&Verify illegal */
#define ABRT_CMD                0x0b    /* Target make the command in error */
#define EQUAL                   0x0c    /* Search Data end with Equal       */
#define VLM_OVRFLW              0x0d    /* Some data are left in buffer     */
#define MISCMP                  0x0e    /* find inequality                  */

#define READ_ERR                -1
#define WRITE_ERR               -2

#define	FIRST_RESET		0x01
#define	USED_EXIST		0x02

/*
 * SENSE_DATA
 */
/*---- valid ----*/
#define SENSE_VALID             0x80    /* Sense data is valid as SCSI2     */
#define SENSE_INVALID           0x00    /* Sense data is invalid as SCSI2   */

/*---- error code ----*/
#define CUR_ERR                 0x70    /* current error                    */
#define DEF_ERR                 0x71    /* specific command error           */

/*---- sense key Information ----*/
#define SNSKEYINFO_LEN          3       /* length of sense key information   */

#define SKSV                    0x80
#define CDB_ILLEGAL             0x40
#define DAT_ILLEGAL             0x00
#define BPV                     0x08
#define BIT_ILLEGAL0            0       /* bit0 is illegal                  */
#define BIT_ILLEGAL1            1       /* bit1 is illegal                  */
#define BIT_ILLEGAL2            2       /* bit2 is illegal                  */
#define BIT_ILLEGAL3            3       /* bit3 is illegal                  */
#define BIT_ILLEGAL4            4       /* bit4 is illegal                  */
#define BIT_ILLEGAL5            5       /* bit5 is illegal                  */
#define BIT_ILLEGAL6            6       /* bit6 is illegal                  */
#define BIT_ILLEGAL7            7       /* bit7 is illegal                  */

/*---- ASC ----*/
#define ASC_NO_INFO             0x00
#define ASC_MISCMP              0x1d
#define ASC_INVLD_CDB           0x24
#define ASC_INVLD_PARA          0x26
#define ASC_LU_NOT_READY	0x04
#define ASC_WRITE_ERR           0x0c
#define ASC_READ_ERR            0x11
#define ASC_LOAD_EJCT_ERR       0x53
#define	ASC_MEDIA_NOT_PRESENT	0x3A
#define	ASC_MEDIA_CHANGED	0x28
#define	ASC_MEDIA_IN_PROCESS	0x04
#define	ASC_WRITE_PROTECT	0x27
#define ASC_LUN_NOT_SUPPORTED	0x25

/*---- ASQC ----*/
#define ASCQ_NO_INFO            0x00
#define	ASCQ_MEDIA_IN_PROCESS	0x01
#define ASCQ_MISCMP             0x00
#define ASCQ_INVLD_CDB          0x00
#define ASCQ_INVLD_PARA         0x02
#define ASCQ_LU_NOT_READY	0x02
#define ASCQ_WRITE_ERR          0x02
#define ASCQ_READ_ERR           0x00
#define ASCQ_LOAD_EJCT_ERR      0x00
#define	ASCQ_WRITE_PROTECT	0x00

struct sense_data_t {
	unsigned char   err_code;	/* error code */
	/* bit7 : valid */
	/*   (1 : SCSI2) */
	/*   (0 : Vendor * specific) */
	/* bit6-0 : error * code */
	/*  (0x70 : current * error) */
	/*  (0x71 : specific command error) */
	unsigned char   seg_no;		/* segment No.                      */
	unsigned char   sense_key;	/* byte5 : ILI                      */
	/* bit3-0 : sense key              */
	unsigned char   info[4];	/* information                       */
	unsigned char   ad_sense_len;	/* additional sense data length     */
	unsigned char   cmd_info[4];	/* command specific information      */
	unsigned char   asc;		/* ASC                              */
	unsigned char   ascq;		/* ASCQ                             */
	unsigned char   rfu;		/* FRU                              */
	unsigned char   sns_key_info[3];/* sense key specific information    */
};

/* PCI Operation Register Address */
#define RTSX_HCBAR		0x00
#define RTSX_HCBCTLR		0x04
#define RTSX_HDBAR		0x08
#define RTSX_HDBCTLR		0x0C
#define RTSX_HAIMR		0x10
#define RTSX_BIPR		0x14
#define RTSX_BIER		0x18

/* Host command buffer control register */
#define STOP_CMD		(0x01 << 28)

/* Host data buffer control register */
#define SDMA_MODE		0x00
#define ADMA_MODE		(0x02 << 26)
#define STOP_DMA		(0x01 << 28)
#define TRIG_DMA		(0x01 << 31)

/* Bus interrupt pending register */
#define CMD_DONE_INT		BIT(31)
#define DATA_DONE_INT		BIT(30)
#define TRANS_OK_INT		BIT(29)
#define TRANS_FAIL_INT		BIT(28)
#define XD_INT			BIT(27)
#define MS_INT			BIT(26)
#define SD_INT			BIT(25)
#define GPIO0_INT		BIT(24)
#define OC_INT			BIT(23)
#define SD_WRITE_PROTECT	BIT(19)
#define XD_EXIST		BIT(18)
#define MS_EXIST		BIT(17)
#define SD_EXIST		BIT(16)
#define DELINK_INT		GPIO0_INT
#define MS_OC_INT		BIT(23)
#define SD_OC_INT		BIT(22)

#define CARD_INT		(XD_INT | MS_INT | SD_INT)
#define NEED_COMPLETE_INT	(DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
#define RTSX_INT		(CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | \
				 GPIO0_INT | OC_INT)

#define CARD_EXIST		(XD_EXIST | MS_EXIST | SD_EXIST)

/* Bus interrupt enable register */
#define CMD_DONE_INT_EN		BIT(31)
#define DATA_DONE_INT_EN	BIT(30)
#define TRANS_OK_INT_EN		BIT(29)
#define TRANS_FAIL_INT_EN	BIT(28)
#define XD_INT_EN		BIT(27)
#define MS_INT_EN		BIT(26)
#define SD_INT_EN		BIT(25)
#define GPIO0_INT_EN		BIT(24)
#define OC_INT_EN		BIT(23)
#define DELINK_INT_EN		GPIO0_INT_EN
#define MS_OC_INT_EN		BIT(23)
#define SD_OC_INT_EN		BIT(22)

#define READ_REG_CMD		0
#define WRITE_REG_CMD		1
#define CHECK_REG_CMD		2

#define HOST_TO_DEVICE		0
#define DEVICE_TO_HOST		1

#define RTSX_RESV_BUF_LEN	4096
#define HOST_CMDS_BUF_LEN	1024
#define HOST_SG_TBL_BUF_LEN	(RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)

#define SD_NR		2
#define MS_NR		3
#define XD_NR		4
#define SPI_NR		7
#define SD_CARD		BIT(SD_NR)
#define MS_CARD		BIT(MS_NR)
#define XD_CARD		BIT(XD_NR)
#define SPI_CARD	BIT(SPI_NR)

#define MAX_ALLOWED_LUN_CNT	8

#define XD_FREE_TABLE_CNT	1200
#define MS_FREE_TABLE_CNT	512

/* Bit Operation */
#define SET_BIT(data, idx)	((data) |= 1 << (idx))
#define CLR_BIT(data, idx)	((data) &= ~(1 << (idx)))
#define CHK_BIT(data, idx)	((data) & (1 << (idx)))

/* SG descriptor */
#define RTSX_SG_INT		0x04
#define RTSX_SG_END		0x02
#define RTSX_SG_VALID		0x01

#define RTSX_SG_NO_OP		0x00
#define RTSX_SG_TRANS_DATA	(0x02 << 4)
#define RTSX_SG_LINK_DESC	(0x03 << 4)

struct rtsx_chip;

typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip,
			u32 sec_addr, u16 sec_cnt);

/* Supported Clock */
enum card_clock	{CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60,
		 CLK_80, CLK_100, CLK_120, CLK_150, CLK_200};

enum <