path: root/drivers/staging/rts5208/rtsx_card.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Driver for Realtek PCI-Express card reader
 *
 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
 *
 * Author:
 *   Wei WANG (wei_wang@realsil.com.cn)
 *   Micky Ching (micky_ching@realsil.com.cn)
 */

#ifndef __REALTEK_RTSX_CARD_H
#define __REALTEK_RTSX_CARD_H

#include "rtsx.h"
#include "rtsx_chip.h"
#include "rtsx_transport.h"
#include "sd.h"

#define SSC_POWER_DOWN		0x01
#define SD_OC_POWER_DOWN	0x02
#define MS_OC_POWER_DOWN	0x04
#define ALL_POWER_DOWN		0x07
#define OC_POWER_DOWN		0x06

#define PMOS_STRG_MASK		0x10
#define PMOS_STRG_800mA		0x10
#define PMOS_STRG_400mA		0x00

#define POWER_OFF		0x03
#define PARTIAL_POWER_ON	0x01
#define POWER_ON		0x00

#define MS_POWER_OFF		0x0C
#define MS_PARTIAL_POWER_ON	0x04
#define MS_POWER_ON		0x00
#define MS_POWER_MASK		0x0C

#define SD_POWER_OFF		0x03
#define SD_PARTIAL_POWER_ON	0x01
#define SD_POWER_ON		0x00
#define SD_POWER_MASK		0x03

#define XD_OUTPUT_EN		0x02
#define SD_OUTPUT_EN		0x04
#define MS_OUTPUT_EN		0x08
#define SPI_OUTPUT_EN		0x10

#define CLK_LOW_FREQ		0x01

#define CLK_DIV_1		0x01
#define CLK_DIV_2		0x02
#define CLK_DIV_4		0x03
#define CLK_DIV_8		0x04

#define SSC_80			0
#define SSC_100			1
#define SSC_120			2
#define SSC_150			3
#define SSC_200			4

#define XD_CLK_EN		0x02
#define SD_CLK_EN		0x04
#define MS_CLK_EN		0x08
#define SPI_CLK_EN		0x10

#define XD_MOD_SEL		1
#define SD_MOD_SEL		2
#define MS_MOD_SEL		3
#define SPI_MOD_SEL		4

#define CHANGE_CLK		0x01

#define	SD_CRC7_ERR			0x80
#define	SD_CRC16_ERR			0x40
#define	SD_CRC_WRITE_ERR		0x20
#define	SD_CRC_WRITE_ERR_MASK		0x1C
#define	GET_CRC_TIME_OUT		0x02
#define	SD_TUNING_COMPARE_ERR		0x01

#define	SD_RSP_80CLK_TIMEOUT		0x01

#define	SD_CLK_TOGGLE_EN		0x80
#define	SD_CLK_FORCE_STOP		0x40
#define	SD_DAT3_STATUS			0x10
#define	SD_DAT2_STATUS			0x08
#define	SD_DAT1_STATUS			0x04
#define	SD_DAT0_STATUS			0x02
#define	SD_CMD_STATUS			0x01

#define	SD_IO_USING_1V8			0x80
#define	SD_IO_USING_3V3			0x7F
#define	TYPE_A_DRIVING			0x00
#define	TYPE_B_DRIVING			0x01
#define	TYPE_C_DRIVING			0x02
#define	TYPE_D_DRIVING			0x03

#define	DDR_FIX_RX_DAT			0x00
#define	DDR_VAR_RX_DAT			0x80
#define	DDR_FIX_RX_DAT_EDGE		0x00
#define	DDR_FIX_RX_DAT_14_DELAY		0x40
#define	DDR_FIX_RX_CMD			0x00
#define	DDR_VAR_RX_CMD			0x20
#define	DDR_FIX_RX_CMD_POS_EDGE		0x00
#define	DDR_FIX_RX_CMD_14_DELAY		0x10
#define	SD20_RX_POS_EDGE		0x00
#define	SD20_RX_14_DELAY		0x08
#define SD20_RX_SEL_MASK		0x08

#define	DDR_FIX_TX_CMD_DAT		0x00
#define	DDR_VAR_TX_CMD_DAT		0x80
#define	DDR_FIX_TX_DAT_14_TSU		0x00
#define	DDR_FIX_TX_DAT_12_TSU		0x40
#define	DDR_FIX_TX_CMD_NEG_EDGE		0x00
#define	DDR_FIX_TX_CMD_14_AHEAD		0x20
#define	SD20_TX_NEG_EDGE		0x00
#define	SD20_TX_14_AHEAD		0x10
#define SD20_TX_SEL_MASK		0x10
#define	DDR_VAR_SDCLK_POL_SWAP		0x01

#define	SD_TRANSFER_START		0x80
#define	SD_TRANSFER_END			0x40
#define SD_STAT_IDLE			0x20
#define	SD_TRANSFER_ERR			0x10
#define	SD_TM_NORMAL_WRITE		0x00
#define	SD_TM_AUTO_WRITE_3		0x01
#define	SD_TM_AUTO_WRITE_4		0x02
#define	SD_TM_AUTO_READ_3		0x05
#define	SD_TM_AUTO_READ_4		0x06
#define	SD_TM_CMD_RSP			0x08
#define	SD_TM_AUTO_WRITE_1		0x09
#define	SD_TM_AUTO_WRITE_2		0x0A
#define	SD_TM_NORMAL_READ		0x0C
#define	SD_TM_AUTO_READ_1		0x0D
#define	SD_TM_AUTO_READ_2		0x0E
#define	SD_TM_AUTO_TUNING		0x0F

#define PHASE_CHANGE			0x80
#define PHASE_NOT_RESET			0x40

#define DCMPS_CHANGE			0x80
#define DCMPS_CHANGE_DONE		0x40
#define DCMPS_ERROR			0x20
#define DCMPS_CURRENT_PHASE		0x1F

#define SD_CLK_DIVIDE_0			0x00
#define	SD_CLK_DIVIDE_256		0xC0
#define	SD_CLK_DIVIDE_128		0x80
#define	SD_BUS_WIDTH_1			0x00
#define	SD_BUS_WIDTH_4			0x01
#define	SD_BUS_WIDTH_8			0x02
#define	SD_ASYNC_FIFO_NOT_RST		0x10
#define	SD_20_MODE			0x00
#define	SD_DDR_MODE			0x04
#define	SD_30_MODE			0x08

#define SD_CLK_DIVIDE_MASK		0xC0

#define SD_CMD_IDLE			0x80

#define SD_DATA_IDLE			0x80

#define DCM_RESET			0x08
#define DCM_LOCKED			0x04
#define DCM_208M			0x00
#define DCM_TX				0x01
#define DCM_RX				0x02

#define DRP_START			0x80
#define DRP_DONE			0x40

#define DRP_WRITE			0x80
#define DRP_READ			0x00
#define DCM_WRITE_ADDRESS_50		0x50
#define DCM_WRITE_ADDRESS_51		0x51
#define DCM_READ_ADDRESS_00		0x00
#define DCM_READ_ADDRESS_51		0x51

#define	SD_CALCULATE_CRC7		0x00
#define	SD_NO_CALCULATE_CRC7		0x80
#define	SD_CHECK_CRC16			0x00
#define	SD_NO_CHECK_CRC16		0x40
#define SD_NO_CHECK_WAIT_CRC_TO		0x20
#define	SD_WAIT_BUSY_END		0x08
#define	SD_NO_WAIT_BUSY_END		0x00
#define	SD_CHECK_CRC7			0x00
#define	SD_NO_CHECK_CRC7		0x04
#define	SD_RSP_LEN_0			0x00
#define	SD_RSP_LEN_6			0x01
#define	SD_RSP_LEN_17			0x02
#define	SD_RSP_TYPE_R0			0x04
#define	SD_RSP_TYPE_R1			0x01
#define	SD_RSP_TYPE_R1b			0x09
#define	SD_RSP_TYPE_R2			0x02
#define	SD_RSP_TYPE_R3			0x05
#define	SD_RSP_TYPE_R4			0x05
#define	SD_RSP_TYPE_R5			0x01
#define	SD_RSP_TYPE_R6			0x01
#define	SD_RSP_TYPE_R7			0x01

#define	SD_RSP_80CLK_TIMEOUT_EN		0x01

#define	SAMPLE_TIME_RISING		0x00
#define	SAMPLE_TIME_FALLING		0x80
#define	PUSH_TIME_DEFAULT		0x00
#define	PUSH_TIME_ODD			0x40
#define	NO_EXTEND_TOGGLE		0x00
#define	EXTEND_TOGGLE_CHK		0x20
#define	MS_BUS_WIDTH_1			0x00
#define	MS_BUS_WIDTH_4			0x10
#define	MS_BUS_WIDTH_8			0x18
#define	MS_2K_SECTOR_MODE		0x04
#define	MS_512_SECTOR_MODE		0x00
#define	MS_TOGGLE_TIMEOUT_EN		0x00
#define	MS_TOGGLE_TIMEOUT_DISEN		0x01
#define MS_NO_CHECK_INT			0x02

#define	WAIT_INT			0x80
#define	NO_WAIT_INT			0x00
#define	NO_AUTO_READ_INT_REG		0x00
#define	AUTO_READ_INT_REG		0x40
#define	MS_CRC16_ERR			0x20
#define	MS_RDY_TIMEOUT			0x10
#define	MS_INT_CMDNK			0x08
#define	MS_INT_BREQ			0x04
#define	MS_INT_ERR			0x02
#define	MS_INT_CED			0x01

#define	MS_TRANSFER_START		0x80
#define	MS_TRANSFER_END			0x40
#define	MS_TRANSFER_ERR			0x20
#define	MS_BS_STATE			0x10
#define	MS_TM_READ_BYTES		0x00
#define	MS_TM_NORMAL_READ		0x01
#define	MS_TM_WRITE_BYTES		0x04
#define	MS_TM_NORMAL_WRITE		0x05
#define	MS_TM_AUTO_READ			0x08
#define	MS_TM_AUTO_WRITE		0x0C

#define CARD_SHARE_MASK			0x0F
#define CARD_SHARE_MULTI_LUN		0x00
#define	CARD_SHARE_NORMAL		0x00
#define	CARD_SHARE_48_XD		0x02
#define	CARD_SHARE_48_SD		0x04
#define	CARD_SHARE_48_MS		0x08
#define CARD_SHARE_BAROSSA_XD		0x00
#define CARD_SHARE_BAROSSA_SD		0x01
#define CARD_SHARE_BAROSSA_MS		0x02

#define	MS_DRIVE_8			0x00
#define	MS_DRIVE_4			0x40
#define	MS_DRIVE_12			0x80
#define	SD_DRIVE_8			0x00
#define	SD_DRIVE_4			0x10
#define	SD_DRIVE_12			0x20
#define	XD_DRIVE_8			0x00
#define	XD_DRIVE_4			0x04
#define	XD_DRIVE_12			0x08

#define SPI_STOP		0x01
#define XD_STOP			0x02
#define SD_STOP			0x04
#define MS_STOP			0x08
#define SPI_CLR_ERR		0x10
#define XD_CLR_ERR		0x20
#define SD_CLR_ERR		0x40
#define MS_CLR_ERR		0x80

#define CRC_FIX_CLK		(0x00 << 0)
#define CRC_VAR_CLK0		(0x01 << 0)
#define CRC_VAR_CLK1		(0x02 << 0)
#define SD30_FIX_CLK		(0x00 << 2)
#define SD30_VAR_CLK0		(0x01 << 2)
#define SD30_VAR_CLK1		(0x02 << 2)
#define SAMPLE_FIX_CLK		(0x00 << 4)
#define SAMPLE_VAR_CLK0		(0x01 << 4)
#define SAMPLE_VAR_CLK1		(0x02 << 4)

#define SDIO_VER_20		0x80
#define SDIO_VER_10		0x00
#define SDIO_VER_CHG		0x40
#define SDIO_BUS_AUTO_SWITCH	0x10

#define PINGPONG_BUFFER		0x01
#define RING_BUFFER		0x00

#define RB_FLUSH		0x80

#define DMA_DONE_INT_EN			0x80
#define SUSPEND_INT_EN			0x40
#define LINK_RDY_INT_EN			0x20
#define LINK_DOWN_INT_EN		0x10

#define DMA_DONE_INT			0x80
#define SUSPEND_INT			0x40
#define LINK_RDY_INT			0x20
#define LINK_DOWN_INT			0x10

#define MRD_ERR_INT_EN			0x40
#define MWR_ERR_INT_EN			0x20
#define SCSI_CMD_INT_EN			0x10
#define TLP_RCV_INT_EN			0x08
#define TLP_TRSMT_INT_EN		0x04
#define MRD_COMPLETE_INT_EN		0x02
#define MWR_COMPLETE_INT_EN		0x01

#define MRD_ERR_INT			0x40
#define MWR_ERR_INT			0x20
#define SCSI_CMD_INT			0x10
#define TLP_RX_INT			0x08
#define TLP_TX_INT			0x04
#define MRD_COMPLETE_INT		0x02
#define MWR_COMPLETE_INT		0x01

#define MSG_RX_INT_EN			0x08
#define MRD_RX_INT_EN			0x04
#define MWR_RX_INT_EN			0x02
#define CPLD_RX_INT_EN			0x01

#define MSG_RX_INT			0x08
#define MRD_RX_INT			0x04
#define MWR_RX_INT			0x02
#define CPLD_RX_INT			0x01

#define MSG_TX_INT_EN			0x08
#define MRD_TX_INT_EN			0x04
#define MWR_TX_INT_EN			0x02
#define CPLD_TX_INT_EN			0x01

#define MSG_TX_INT			0x08
#define MRD_TX_INT			0x04
#define MWR_TX_INT			0x02
#define CPLD_TX_INT			0x01

#define DMA_RST				0x80
#define DMA_BUSY			0x04
#define DMA_DIR_TO_CARD			0x00
#define DMA_DIR_FROM_CARD		0x02
#define DMA_EN				0x01
#define DMA_128				(0 << 4)
#define DMA_256				(1 << 4)
#define DMA_512				(2 << 4)
#define DMA_1024			(3 << 4)
#define DMA_PACK_SIZE_MASK		0x30

#define	XD_PWR_OFF_DELAY0		0x00
#define	XD_PWR_OFF_DELAY1		0x02
#define	XD_PWR_OFF_DELAY2		0x04
#define	XD_PWR_OFF_DELAY3		0x06
#define	XD_AUTO_PWR_OFF_EN		0xF7
#define	XD_NO_AUTO_PWR_OFF		0x08

#define	XD_TIME_RWN_1			0x00
#define	XD_TIME_RWN_STEP		0x20
#define	XD_TIME_RW_1			0x00
#define	XD_TIME_RW_STEP			0x04
#define	XD_TIME_SETUP_1			0x00
#define	XD_TIME_SETUP_STEP		0x01

#define	XD_ECC2_UNCORRECTABLE		0x80
#define	XD_ECC2_ERROR			0x40
#define	XD_ECC1_UNCORRECTABLE		0x20
#define	XD_ECC1_ERROR			0x10
#define	XD_RDY				0x04
#define	XD_CE_EN			0xFD
#define	XD_CE_DISEN			0x02
#define	XD_WP_EN			0xFE
#define	XD_WP_DISEN			0x01

#define	XD_TRANSFER_START		0x80
#define	XD_TRANSFER_END			0x40
#define	XD_PPB_EMPTY			0x20
#define	XD_RESET			0x00
#define	XD_ERASE			0x01
#define	XD_READ_STATUS			0x02
#define	XD_READ_ID			0x03
#define	XD_READ_REDUNDANT		0x04
#define	XD_READ_PAGES			0x05
#define	XD_SET_CMD			0x06
#define	XD_NORMAL_READ			0x07
#define	XD_WRITE_PAGES			0x08
#define	XD_NORMAL_WRITE			0x09
#define	XD_WRITE_REDUNDANT		0x0A
#define	XD_SET_ADDR			0x0B

#define	XD_PPB_TO_SIE			0x80
#define	XD_TO_PPB_ONLY			0x00
#define	XD_BA_TRANSFORM			0x40
#define	XD_BA_NO_TRANSFORM		0x00
#define	XD_NO_CALC_ECC			0x20
#define	XD_CALC_ECC			0x00
#define	XD_IGNORE_ECC			0x10
#define	XD_CHECK_ECC			0x00
#define	XD_DIRECT_TO_RB			0x08
#define	XD_ADDR_LENGTH_0		0x00
#define	XD_ADDR_LENGTH_1		0x01
#define	XD_ADDR_LENGTH_2		0x02
#define	XD_ADDR_LENGTH_3		0x03
#define	XD_ADDR_LENGTH_4		0x04

#define	XD_GPG				0xFF
#define	XD_BPG				0x00

#define	XD_GBLK				0xFF
#define	XD_LATER_BBLK			0xF0

#define	XD_ECC2_ALL1			0x80
#define	XD_ECC1_ALL1			0x40
#define	XD_BA2_ALL0			0x20
#define	XD_BA1_ALL0			0x10
#define	XD_BA1_BA2_EQL			0x04
#define	XD_BA2_VALID			0x02
#define	XD_BA1_VALID			0x01

#define	XD_PGSTS_ZEROBIT_OVER4		0x00
#define	XD_PGSTS_NOT_FF			0x02
#define	XD_AUTO_CHK_DATA_STATUS		0x01

#define	RSTB_MODE_DETECT		0x80
#define	MODE_OUT_VLD			0x40
#define	MODE_OUT_0_NONE			0x00
#defin