path: root/drivers/staging/rtlwifi/halmac/halmac_reg2.h

/******************************************************************************
 *
 * Copyright(c) 2016  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/
#ifndef __HALMAC_COM_REG_H__
#define __HALMAC_COM_REG_H__
/*-------------------------Modification Log-----------------------------------
 *	For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524
 *	The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A
 *	8812A and 8188E is not included in page0 register
 *
 *	For other pages, it is based on MAC_Register.doc SVN502
 *	Most IC is the same with 8812A
 *-------------------------Modification Log-----------------------------------
 */

/*--------------------------Include File--------------------------------------*/
/*--------------------------Include File--------------------------------------*/

#define REG_SYS_ISO_CTRL				0x0000

#define REG_SDIO_TX_CTRL				0x10250000

#define REG_SYS_FUNC_EN				0x0002
#define REG_SYS_PW_CTRL				0x0004
#define REG_SYS_CLK_CTRL				0x0008
#define REG_SYS_EEPROM_CTRL				0x000A
#define REG_EE_VPD					0x000C
#define REG_SYS_SWR_CTRL1				0x0010
#define REG_SYS_SWR_CTRL2				0x0014

#define REG_SDIO_HIMR					0x10250014

#define REG_SYS_SWR_CTRL3				0x0018

#define REG_SDIO_HISR					0x10250018

#define REG_RSV_CTRL					0x001C

#define REG_SDIO_RX_REQ_LEN				0x1025001C

#define REG_RF_CTRL					0x001F

#define REG_SDIO_FREE_TXPG_SEQ_V1			0x1025001F

#define REG_AFE_LDO_CTRL				0x0020

#define REG_SDIO_FREE_TXPG				0x10250020

#define REG_AFE_CTRL1					0x0024

#define REG_SDIO_FREE_TXPG2				0x10250024

#define REG_AFE_CTRL2					0x0028

#define REG_SDIO_OQT_FREE_TXPG_V1			0x10250028

#define REG_AFE_CTRL3					0x002C
#define REG_EFUSE_CTRL					0x0030

#define REG_SDIO_HTSFR_INFO				0x10250030

#define REG_LDO_EFUSE_CTRL				0x0034
#define REG_PWR_OPTION_CTRL				0x0038

#define REG_SDIO_HCPWM1_V2				0x10250038
#define REG_SDIO_HCPWM2_V2				0x1025003A

#define REG_CAL_TIMER					0x003C
#define REG_ACLK_MON					0x003E
#define REG_GPIO_MUXCFG				0x0040

#define REG_SDIO_INDIRECT_REG_CFG			0x10250040

#define REG_GPIO_PIN_CTRL				0x0044

#define REG_SDIO_INDIRECT_REG_DATA			0x10250044

#define REG_GPIO_INTM					0x0048
#define REG_LED_CFG					0x004C
#define REG_FSIMR					0x0050
#define REG_FSISR					0x0054
#define REG_HSIMR					0x0058
#define REG_HSISR					0x005C
#define REG_GPIO_EXT_CTRL				0x0060

#define REG_SDIO_H2C					0x10250060

#define REG_PAD_CTRL1					0x0064

#define REG_SDIO_C2H					0x10250064

#define REG_WL_BT_PWR_CTRL				0x0068

#define REG_SDM_DEBUG					0x006C

#define REG_SYS_SDIO_CTRL				0x0070

#define REG_HCI_OPT_CTRL				0x0074

#define REG_AFE_CTRL4					0x0078

#define REG_LDO_SWR_CTRL				0x007C

#define REG_MCUFW_CTRL					0x0080

#define REG_SDIO_HRPWM1				0x10250080
#define REG_SDIO_HRPWM2				0x10250082

#define REG_MCU_TST_CFG				0x0084

#define REG_SDIO_HPS_CLKR				0x10250084
#define REG_SDIO_BUS_CTRL				0x10250085

#define REG_SDIO_HSUS_CTRL				0x10250086

#define REG_HMEBOX_E0_E1				0x0088

#define REG_SDIO_RESPONSE_TIMER			0x10250088

#define REG_SDIO_CMD_CRC				0x1025008A

#define REG_HMEBOX_E2_E3				0x008C
#define REG_WLLPS_CTRL					0x0090

#define REG_SDIO_HSISR					0x10250090
#define REG_SDIO_HSIMR					0x10250091

#define REG_AFE_CTRL5					0x0094

#define REG_GPIO_DEBOUNCE_CTRL				0x0098
#define REG_RPWM2					0x009C
#define REG_SYSON_FSM_MON				0x00A0

#define REG_AFE_CTRL6					0x00A4

#define REG_PMC_DBG_CTRL1				0x00A8

#define REG_AFE_CTRL7					0x00AC

#define REG_HIMR0					0x00B0
#define REG_HISR0					0x00B4
#define REG_HIMR1					0x00B8
#define REG_HISR1					0x00BC
#define REG_DBG_PORT_SEL				0x00C0

#define REG_SDIO_ERR_RPT				0x102500C0
#define REG_SDIO_CMD_ERRCNT				0x102500C1
#define REG_SDIO_DATA_ERRCNT				0x102500C2

#define REG_PAD_CTRL2					0x00C4

#define REG_SDIO_CMD_ERR_CONTENT			0x102500C4

#define REG_SDIO_CRC_ERR_IDX				0x102500C9
#define REG_SDIO_DATA_CRC				0x102500CA
#define REG_SDIO_DATA_REPLY_TIME			0x102500CB

#define REG_PMC_DBG_CTRL2				0x00CC
#define REG_BIST_CTRL					0x00D0
#define REG_BIST_RPT					0x00D4
#define REG_MEM_CTRL					0x00D8

#define REG_AFE_CTRL8					0x00DC

#define REG_USB_SIE_INTF				0x00E0
#define REG_PCIE_MIO_INTF				0x00E4
#define REG_PCIE_MIO_INTD				0x00E8

#define REG_WLRF1					0x00EC

#define REG_SYS_CFG1					0x00F0
#define REG_SYS_STATUS1				0x00F4
#define REG_SYS_STATUS2				0x00F8
#define REG_SYS_CFG2					0x00FC
#define REG_CR						0x0100

#define REG_PKT_BUFF_ACCESS_CTRL			0x0106

#define REG_TSF_CLK_STATE				0x0108
#define REG_TXDMA_PQ_MAP				0x010C
#define REG_TRXFF_BNDY					0x0114

#define REG_PTA_I2C_MBOX				0x0118

#define REG_RXFF_BNDY					0x011C

#define REG_FE1IMR					0x0120

#define REG_FE1ISR					0x0124

#define REG_CPWM					0x012C
#define REG_FWIMR					0x0130
#define REG_FWISR					0x0134
#define REG_FTIMR					0x0138
#define REG_FTISR					0x013C
#define REG_PKTBUF_DBG_CTRL				0x0140
#define REG_PKTBUF_DBG_DATA_L				0x0144
#define REG_PKTBUF_DBG_DATA_H				0x0148
#define REG_CPWM2					0x014C
#define REG_TC0_CTRL					0x0150
#define REG_TC1_CTRL					0x0154
#define REG_TC2_CTRL					0x0158
#define REG_TC3_CTRL					0x015C
#define REG_TC4_CTRL					0x0160
#define REG_TCUNIT_BASE				0x0164
#define REG_TC5_CTRL					0x0168
#define REG_TC6_CTRL					0x016C
#define REG_MBIST_FAIL					0x0170
#define REG_MBIST_START_PAUSE				0x0174
#define REG_MBIST_DONE					0x0178

#define REG_MBIST_FAIL_NRML				0x017C

#define REG_AES_DECRPT_DATA				0x0180
#define REG_AES_DECRPT_CFG				0x0184

#define REG_TMETER					0x0190
#define REG_OSC_32K_CTRL				0x0194
#define REG_32K_CAL_REG1				0x0198
#define REG_C2HEVT					0x01A0

#define REG_C2HEVT_1					0x01A4
#define REG_C2HEVT_2					0x01A8
#define REG_C2HEVT_3					0x01AC

#define REG_SW_DEFINED_PAGE1				0x01B8

#define REG_MCUTST_I					0x01C0
#define REG_MCUTST_II					0x01C4
#define REG_FMETHR					0x01C8
#define REG_HMETFR					0x01CC
#define REG_HMEBOX0					0x01D0
#define REG_HMEBOX1					0x01D4
#define REG_HMEBOX2					0x01D8
#define REG_HMEBOX3					0x01DC
#define REG_LLT_INIT					0x01E0

#define REG_LLT_INIT_ADDR				0x01E4

#define REG_BB_ACCESS_CTRL				0x01E8
#define REG_BB_ACCESS_DATA				0x01EC
#define REG_HMEBOX_E0					0x01F0
#define REG_HMEBOX_E1					0x01F4
#define REG_HMEBOX_E2					0x01F8
#define REG_HMEBOX_E3					0x01FC

#define REG_FIFOPAGE_CTRL_1				0x0200

#define REG_FIFOPAGE_CTRL_2				0x0204

#define REG_AUTO_LLT_V1				0x0208

#define REG_TXDMA_OFFSET_CHK				0x020C
#define REG_TXDMA_STATUS				0x0210

#define REG_TX_DMA_DBG					0x0214

#define REG_TQPNT1					0x0218
#define REG_TQPNT2					0x021C

#define REG_TQPNT3					0x0220

#define REG_TQPNT4					0x0224

#define REG_RQPN_CTRL_1				0x0228
#define REG_RQPN_CTRL_2				0x022C
#define REG_FIFOPAGE_INFO_1				0x0230
#define REG_FIFOPAGE_INFO_2				0x0234
#define REG_FIFOPAGE_INFO_3				0x0238
#define REG_FIFOPAGE_INFO_4				0x023C
#define REG_FIFOPAGE_INFO_5				0x0240

#define REG_H2C_HEAD					0x0244
#define REG_H2C_TAIL					0x0248
#define REG_H2C_READ_ADDR				0x024C
#define REG_H2C_WR_ADDR				0x0250
#define REG_H2C_INFO					0x0254

#define REG_RXDMA_AGG_PG_TH				0x0280
#define REG_RXPKT_NUM					0x0284
#define REG_RXDMA_STATUS				0x0288
#define REG_RXDMA_DPR					0x028C
#define REG_RXDMA_MODE					0x0290
#define REG_C2H_PKT					0x0294

#define REG_FWFF_C2H					0x0298
#define REG_FWFF_CTRL					0x029C
#define REG_FWFF_PKT_INFO				0x02A0

#define REG_PCIE_CTRL					0x0300

#define REG_INT_MIG					0x0304
#define REG_BCNQ_TXBD_DESA				0x0308
#define REG_MGQ_TXBD_DESA				0x0310
#define REG_VOQ_TXBD_DESA				0x0318
#define REG_VIQ_TXBD_DESA				0x0320
#define REG_BEQ_TXBD_DESA				0x0328
#define REG_BKQ_TXBD_DESA				0x0330
#define REG_RXQ_RXBD_DESA				0x0338
#define REG_HI0Q_TXBD_DESA				0x0340
#define REG_HI1Q_TXBD_DESA				0x0348
#define REG_HI2Q_TXBD_DESA				0x0350
#define REG_HI3Q_TXBD_DESA				0x0358
#define REG_HI4Q_TXBD_DESA				0x0360
#define REG_HI5Q_TXBD_DESA				0x0368
#define REG_HI6Q_TXBD_DESA				0x0370
#define REG_HI7Q_TXBD_DESA				0x0378
#define REG_MGQ_TXBD_NUM				0x0380
#define REG_RX_RXBD_NUM				0x0382
#define REG_VOQ_TXBD_NUM				0x0384
#define REG_VIQ_TXBD_NUM				0x0386
#define REG_BEQ_TXBD_NUM				0x0388
#define REG_BKQ_TXBD_NUM				0x038A
#define REG_HI0Q_TXBD_NUM				0x038C
#define REG_HI1Q_TXBD_NUM				0x038E
#define REG_HI2Q_TXBD_NUM				0x0390
#define REG_HI3Q_TXBD_NUM				0x0392
#define REG_HI4Q_TXBD_NUM				0x0394
#define REG_HI5Q_TXBD_NUM				0x0396
#define REG_HI6Q_TXBD_NUM				0x0398
#define REG_HI7Q_TXBD_NUM				0x039A
#define REG_TSFTIMER_HCI				0x039C
#define REG_BD_RWPTR_CLR				0x039C
#define REG_VOQ_TXBD_IDX				0x03A0
#define REG_VIQ_TXBD_IDX				0x03A4
#define REG_BEQ_TXBD_IDX				0x03A8
#define REG_BKQ_TXBD_IDX				0x03AC
#define REG_MGQ_TXBD_IDX				0x03B0
#define REG_RXQ_RXBD_IDX				0x03B4
#define REG_HI0Q_TXBD_IDX				0x03B8
#define REG_HI1Q_TXBD_IDX				0x03BC
#define REG_HI2Q_TXBD_IDX				0x03C0
#define REG_HI3Q_TXBD_IDX				0x03C4
#define REG_HI4Q_TXBD_IDX				0x03C8
#define REG_HI5Q_TXBD_IDX				0x03CC
#define REG_HI6Q_TXBD_IDX				0x03D0
#define REG_HI7Q_TXBD_IDX				0x03D4

#define REG_DBG_SEL_V1					0x03D8

#define REG_PCIE_HRPWM1_V1				0x03D9

#define REG_PCIE_HCPWM1_V1				0x03DA

#define REG_PCIE_CTRL2					0x03DB

#define REG_PCIE_HRPWM2_V1				0x03DC

#define REG_PCIE_HCPWM2_V1				0x03DE

#define REG_PCIE_H2C_MSG_V1				0x03E0

#define REG_PCIE_C2H_MSG_V1				0x03E4

#define REG_DBI_WDATA_V1				0x03E8

#define REG_DBI_RDATA_V1				0x03EC

#define REG_DBI_FLAG_V1				0x03F0

#define REG_MDIO_V1					0x03F4

#define REG_PCIE_MIX_CFG				0x03F8

#define REG_HCI_MIX_CFG				0x03FC

#define REG_Q0_INFO					0x0400
#define REG_Q1_INFO					0x0404
#define REG_Q2_INFO					0x0408
#define REG_Q3_INFO					0x040C
#define REG_MGQ_INFO					0x0410
#define REG_HIQ_INFO					0x0414
#define REG_BCNQ_INFO					0x0418
#define REG_TXPKT_EMPTY				0x041A
#define REG_CPU_MGQ_INFO				0x041C
#define REG_FWHW_TXQ_CTRL				0x0420