path: root/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h

/*****************************************************************************
 *	Copyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.
 *
 * Module:	__INC_HAL8192SPHYREG_H
 *
 *
 * Note:	1. Define PMAC/BB register map
 *			2. Define RF register map
 *			3. PMAC/BB register bit mask.
 *			4. RF reg bit mask.
 *			5. Other BB/RF relative definition.
 *
 *
 * Export:	Constants, macro, functions(API), global variables(None).
 *
 * Abbrev:
 *
 * History:
 *	Data			Who		Remark
 *	08/07/2007	MHC		1. Porting from 9x series PHYCFG.h.
 *						2. Reorganize code architecture.
 *	09/25/2008	MH		1. Add RL6052 register definition
 *
 *****************************************************************************/
#ifndef __RTL871X_MP_PHY_REGDEF_H
#define __RTL871X_MP_PHY_REGDEF_H


/*--------------------------Define Parameters-------------------------------*/

/*============================================================
 *       8192S Regsiter offset definition
 *============================================================
 *
 *
 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
 * 3. RF register 0x00-2E
 * 4. Bit Mask for BB/RF register
 * 5. Other definition for BB/RF R/W
 *
 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
 * 1. Page1(0x100)
 */
#define	rPMAC_Reset			0x100
#define	rPMAC_TxStart			0x104
#define	rPMAC_TxLegacySIG		0x108
#define	rPMAC_TxHTSIG1			0x10c
#define	rPMAC_TxHTSIG2			0x110
#define	rPMAC_PHYDebug			0x114
#define	rPMAC_TxPacketNum		0x118
#define	rPMAC_TxIdle			0x11c
#define	rPMAC_TxMACHeader0		0x120
#define	rPMAC_TxMACHeader1		0x124
#define	rPMAC_TxMACHeader2		0x128
#define	rPMAC_TxMACHeader3		0x12c
#define	rPMAC_TxMACHeader4		0x130
#define	rPMAC_TxMACHeader5		0x134
#define	rPMAC_TxDataType		0x138
#define	rPMAC_TxRandomSeed		0x13c
#define	rPMAC_CCKPLCPPreamble		0x140
#define	rPMAC_CCKPLCPHeader		0x144
#define	rPMAC_CCKCRC16			0x148
#define	rPMAC_OFDMRxCRC32OK		0x170
#define	rPMAC_OFDMRxCRC32Er		0x174
#define	rPMAC_OFDMRxParityEr		0x178
#define	rPMAC_OFDMRxCRC8Er		0x17c
#define	rPMAC_CCKCRxRC16Er		0x180
#define	rPMAC_CCKCRxRC32Er		0x184
#define	rPMAC_CCKCRxRC32OK		0x188
#define	rPMAC_TxStatus			0x18c

/*
 * 2. Page2(0x200)
 *
 * The following two definition are only used for USB interface.
 *#define RF_BB_CMD_ADDR	0x02c0	// RF/BB read/write command address.
 *#define RF_BB_CMD_DATA	0x02c4	// RF/BB read/write command data.
 *
 *
 * 3. Page8(0x800)
 */
#define	rFPGA0_RFMOD			0x800	/*RF mode & CCK TxSC RF
						 * BW Setting?? */
#define	rFPGA0_TxInfo			0x804	/* Status report?? */
#define	rFPGA0_PSDFunction		0x808
#define	rFPGA0_TxGainStage		0x80c	/* Set TX PWR init gain? */
#define	rFPGA0_RFTiming1		0x810	/* Useless now */
#define	rFPGA0_RFTiming2		0x814
#define	rFPGA0_XA_HSSIParameter1	0x820	/* RF 3 wire register */
#define	rFPGA0_XA_HSSIParameter2	0x824
#define	rFPGA0_XB_HSSIParameter1	0x828
#define	rFPGA0_XB_HSSIParameter2	0x82c
#define	rFPGA0_XC_HSSIParameter1	0x830
#define	rFPGA0_XC_HSSIParameter2	0x834
#define	rFPGA0_XD_HSSIParameter1	0x838
#define	rFPGA0_XD_HSSIParameter2	0x83c
#define	rFPGA0_XA_LSSIParameter		0x840
#define	rFPGA0_XB_LSSIParameter		0x844
#define	rFPGA0_XC_LSSIParameter		0x848
#define	rFPGA0_XD_LSSIParameter		0x84c

#define	rFPGA0_RFWakeUpParameter	0x850	/* Useless now */
#define	rFPGA0_RFSleepUpParameter	0x854

#define	rFPGA0_XAB_SwitchControl	0x858	/* RF Channel switch */
#define	rFPGA0_XCD_SwitchControl	0x85c

#define	rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
#define	rFPGA0_XB_RFInterfaceOE		0x864
#define	rFPGA0_XC_RFInterfaceOE		0x868
#define	rFPGA0_XD_RFInterfaceOE		0x86c
#define	rFPGA0_XAB_RFInterfaceSW	0x870	/* RF Interface Software Ctrl */
#define	rFPGA0_XCD_RFInterfaceSW	0x874

#define	rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
#define	rFPGA0_XCD_RFParameter		0x87c

#define	rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting
						 * RF-R/W protection
						 * for parameter4?? */
#define	rFPGA0_AnalogParameter2		0x884
#define	rFPGA0_AnalogParameter3		0x888	/* Useless now */
#define	rFPGA0_AnalogParameter4		0x88c

#define	rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
#define	rFPGA0_XB_LSSIReadBack		0x8a4
#define	rFPGA0_XC_LSSIReadBack		0x8a8
#define	rFPGA0_XD_LSSIReadBack		0x8ac

#define	rFPGA0_PSDReport		0x8b4	/* Useless now */
#define	rFPGA0_XAB_RFInterfaceRB	0x8e0	/* Useless now */
#define	rFPGA0_XCD_RFInterfaceRB	0x8e4	/* Useless now */

/*
 * 4. Page9(0x900)
 */
#define	rFPGA1_RFMOD			0x900	/* RF mode & OFDM TxSC */

#define	rFPGA1_TxBlock			0x904	/* Useless now */
#define	rFPGA1_DebugSelect		0x908	/* Useless now */
#define	rFPGA1_TxInfo			0x90c	/* Useless now */

/*
 * 5. PageA(0xA00)
 *
 * Set Control channel to upper or lower.
 * These settings are required only for 40MHz */
#define	rCCK0_System			0xa00

#define	rCCK0_AFESetting		0xa04	/* Disable init gain now */
#define	rCCK0_CCA			0xa08	/* Disable init gain now */

#define	rCCK0_RxAGC1			0xa0c
/* AGC default value, saturation level
 * Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now.
 * Not the same as 90 series */
#define	rCCK0_RxAGC2			0xa10	/* AGC & DAGC */

#define	rCCK0_RxHP			0xa14

#define	rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel
						 * estimation threshold */
#define	rCCK0_DSPParameter2		0xa1c	/* SQ threshold */

#define	rCCK0_TxFilter1			0xa20
#define	rCCK0_TxFilter2			0xa24
#define	rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
#define	rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d useless now 0xa30-a4f
						 * channel report */
#define	rCCK0_TRSSIReport		0xa50
#define	rCCK0_RxReport			0xa54   /* 0xa57 */
#define	rCCK0_FACounterLower		0xa5c   /* 0xa5b */
#define	rCCK0_FACounterUpper		0xa58   /* 0xa5c */

/*
 * 6. PageC(0xC00)
 */
#define	rOFDM0_LSTF			0xc00
#define	rOFDM0_TRxPathEnable		0xc04
#define	rOFDM0_TRMuxPar			0xc08
#define	rOFDM0_TRSWIsolation		0xc0c

/*RxIQ DC offset, Rx digital filter, DC notch filter */
#define	rOFDM0_XARxAFE			0xc10
#define	rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
#define	rOFDM0_XBRxAFE			0xc18
#define	rOFDM0_XBRxIQImbalance		0xc1c
#define	rOFDM0_XCRxAFE			0xc20
#define	rOFDM0_XCRxIQImbalance		0xc24
#define	rOFDM0_XDRxAFE			0xc28
#define	rOFDM0_XDRxIQImbalance		0xc2c

#define	rOFDM0_RxDetector1		0xc30  /* PD,BW & SBD DM tune
						* init gain */
#define	rOFDM0_RxDetector2		0xc34  /* SBD & Fame Sync. */
#define	rOFDM0_RxDetector3		0xc38  /* Frame Sync. */
#define	rOFDM0_RxDetector4		0xc3c  /* PD, SBD, Frame Sync &
						* Short-GI */

#define	rOFDM0_RxDSP			0xc40  /* Rx Sync Path */
#define	rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
#define	rOFDM0_CCADropThreshold		0xc48 /* CCA Drop threshold */
#define	rOFDM0_ECCAThreshold		0xc4c /* energy CCA */

#define	rOFDM0_XAAGCCore1		0xc50	/* DIG */
#define	rOFDM0_XAAGCCore2		0xc54
#define	rOFDM0_XBAGCCore1		0xc58
#define	rOFDM0_XBAGCCore2		0xc5c
#define	rOFDM0_XCAGCCore1		0xc60
#define	rOFDM0_XCAGCCore2		0xc64
#define	rOFDM0_XDAGCCore1		0xc68
#define	rOFDM0_XDAGCCore2		0xc6c
#define	rOFDM0_AGCParameter1		0xc70
#define	rOFDM0_AGCParameter2		0xc74
#define	rOFDM0_AGCRSSITable		0xc78
#define	rOFDM0_HTSTFAGC			0xc7c

#define	rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
#define	rOFDM0_XATxAFE			0xc84
#define	rOFDM0_XBTxIQImbalance		0xc88
#define	rOFDM0_XBTxAFE			0xc8c
#define	rOFDM0_XCTxIQImbalance		0xc90
#define	rOFDM0_XCTxAFE			0xc94
#define	rOFDM0_XDTxIQImbalance		0xc98
#define	rOFDM0_XDTxAFE			0xc9c

#define	rOFDM0_RxHPParameter		0xce0
#define	rOFDM0_TxPseudoNoiseWgt		0xce4
#define	rOFDM0_FrameSync		0xcf0
#define	rOFDM0_DFSReport		0xcf4
#define	rOFDM0_TxCoeff1			0xca4
#define	rOFDM0_TxCoeff2			0xca8
#define	rOFDM0_TxCoeff3			0xcac
#define	rOFDM0_TxCoeff4			0xcb0
#define	rOFDM0_TxCoeff5			0xcb4
#define	rOFDM0_TxCoeff6			0xcb8

/*
 * 7. PageD(0xD00)
 */
#define	rOFDM1_LSTF			0xd00
#define	rOFDM1_TRxPathEnable		0xd04

#define	rOFDM1_CFO			0xd08	/* No setting now */
#define	rOFDM1_CSI1			0xd10
#define	rOFDM1_SBD			0xd14
#define	rOFDM1_CSI2			0xd18
#define	rOFDM1_CFOTracking		0xd2c
#define	rOFDM1_TRxMesaure1		0xd34
#define	rOFDM1_IntfDet			0xd3c
#define	rOFDM1_PseudoNoiseStateAB	0xd50
#define	rOFDM1_PseudoNoiseStateCD	0xd54
#define	rOFDM1_RxPseudoNoiseWgt		0xd58

#define	rOFDM_PHYCounter1		0xda0  /* cca, parity fail */
#define	rOFDM_PHYCounter2		0xda4  /* rate illegal, crc8 fail */
#define	rOFDM_PHYCounter3		0xda8  /* MCS not support */
#define	rOFDM_ShortCFOAB		0xdac  /* No setting now */
#define	rOFDM_ShortCFOCD		0xdb0
#define	rOFDM_LongCFOAB			0xdb4
#define	rOFDM_LongCFOCD			0xdb8
#define	rOFDM_TailCFOAB			0xdbc
#define	rOFDM_TailCFOCD			0xdc0
#define	rOFDM_PWMeasure1		0xdc4
#define	rOFDM_PWMeasure2		0xdc8
#define	rOFDM_BWReport			0xdcc
#define	rOFDM_AGCReport			0xdd0
#define	rOFDM_RxSNR			0xdd4
#define	rOFDM_RxEVMCSI			0xdd8
#define	rOFDM_SIGReport			0xddc

/*
 * 8. PageE(0xE00)
 */
#define	rTxAGC_Rate18_06		0xe00
#define	rTxAGC_Rate54_24		0xe04
#define	rTxAGC_CCK_Mcs32		0xe08
#define	rTxAGC_Mcs03_Mcs00		0xe10
#define	rTxAGC_Mcs07_Mcs04		0xe14
#define	rTxAGC_Mcs11_Mcs08		0xe18
#define	rTxAGC_Mcs15_Mcs12		0xe1c

/* Analog- control in RX_WAIT_CCA : REG: EE0
 * [Analog- Power & Control Register] */
#define		rRx_Wait_CCCA		0xe70
#define	rAnapar_Ctrl_BB			0xee0

/*
 * 7. RF Register 0x00-0x2E (RF 8256)
 *    RF-0222D 0x00-3F
 *
 * Zebra1
 */
#define	rZebra1_HSSIEnable		0x0	/* Useless now */
#define	rZebra1_TRxEnable1		0x1
#define	rZebra1_TRxEnable2		0x2
#define	rZebra1_AGC			0x4
#define	rZebra1_ChargePump		0x5
#define	rZebra1_Channel			0x7	/* RF channel switch */
#define	rZebra1_TxGain			0x8	/* Useless now */
#define	rZebra1_TxLPF			0x9
#define	rZebra1_RxLPF			0xb
#define	rZebra1_RxHPFCorner		0xc

/* Zebra4 */
#define	rGlobalCtrl			0	/* Useless now */
#define	rRTL8256_TxLPF			19
#define	rRTL8256_RxLPF			11

/* RTL8258 */
#define	rRTL8258_TxLPF			0x11	/* Useless now */
#define	rRTL8258_RxLPF			0x13
#define	rRTL8258_RSSILPF		0xa

/* RL6052 Register definition */
#define	RF_AC				0x00
#define	RF_IQADJ_G1			0x01
#define	RF_IQADJ_G2			0x02
#define	RF_POW_TRSW			0x05

#define	RF_GAIN_RX			0x06
#define	RF_GAIN_TX			0x07

#define	RF_TXM_IDAC			0x08
#define	RF_BS_IQGEN			0x0F

#define	RF_MODE1			0x10
#define	RF_MODE2			0x11

#define	RF_RX_AGC_HP			0x12
#define	RF_TX_AGC			0x13
#define	RF_BIAS				0x14
#define	RF_IPA				0x15
#define	RF_POW_ABILITY			0x17
#define	RF_MODE_AG			0x18
#define	rRfChannel			0x18	/* RF channel and BW switch */
#define	RF_CHNLBW			0x18	/* RF channel and BW switch */
#define	RF_TOP				0x19
#define	RF_RX_G1			0x1A
#define	RF_RX_G2			0x1B
#define	RF_RX_BB2			0x1C
#define	RF_RX_BB1			0x1D

#define	RF_RCK1				0x1E
#define	RF_RCK2				0x1F

#define	RF_TX_G1			0x20
#define	RF_TX_G2			0x21
#define	RF_TX_G3			0x22

#define	RF_TX_BB1			0x23
#define	RF_T_METER			0x24

#define	RF_SYN_G1			0x25	/* RF TX Power control */
#define	RF_SYN_G2			0x26	/* RF TX Power control */
#define	RF_SYN_G3			0x27	/* RF TX Power control */
#define	RF_SYN_G4			0x28	/* RF TX Power control */
#define	RF_SYN_G5			0x29	/* RF TX Power control */
#define	RF_SYN_G6			0x2A	/* RF TX Power control */
#define	RF_SYN_G7			0x2B	/* RF TX Power control */
#define	RF_SYN_G8			0x2C	/* RF TX Power control */

#define	RF_RCK_OS			0x30	/* RF TX PA control */

#define	RF_TXPA_G1			0x31	/* RF TX PA control */
#define	RF_TXPA_G2			0x32	/* RF TX PA control */
#define	RF_TXPA_G3			0x33	/* RF TX PA control */

/*
 * Bit Mask
 *
 * 1. Page1(0x100) */
#define	bBBResetB			0x100	/* Useless now? */
#define	bGlobalResetB			0x200
#define	bOFDMTxStart			0x4
#define	bCCKTxStart			0x8
#define	bCRC32Debug			0x100
#define	bPMACLoopback			0x10
#define	bTxLSIG				0xffffff
#define	bOFDMTxRate			0xf
#define	bOFDMTxReserved			0x10
#define	bOFDMTxLength			0x1ffe0
#define	bOFDMTxParity			0x20000
#define	bTxHTSIG1			0xffffff
#define	bTxHTMCSRate			0x7f