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/*
* Copyright (c) 2003-2012 Broadcom Corporation
* All Rights Reserved
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the Broadcom
* license below:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* #define MAC_SPLIT_MODE */
#define MAC_SPACING 0x400
#define XGMAC_SPACING 0x400
/* PE-MCXMAC register and bit field definitions */
#define R_MAC_CONFIG_1 0x00
#define O_MAC_CONFIG_1__srst 31
#define O_MAC_CONFIG_1__simr 30
#define O_MAC_CONFIG_1__hrrmc 18
#define W_MAC_CONFIG_1__hrtmc 2
#define O_MAC_CONFIG_1__hrrfn 16
#define W_MAC_CONFIG_1__hrtfn 2
#define O_MAC_CONFIG_1__intlb 8
#define O_MAC_CONFIG_1__rxfc 5
#define O_MAC_CONFIG_1__txfc 4
#define O_MAC_CONFIG_1__srxen 3
#define O_MAC_CONFIG_1__rxen 2
#define O_MAC_CONFIG_1__stxen 1
#define O_MAC_CONFIG_1__txen 0
#define R_MAC_CONFIG_2 0x01
#define O_MAC_CONFIG_2__prlen 12
#define W_MAC_CONFIG_2__prlen 4
#define O_MAC_CONFIG_2__speed 8
#define W_MAC_CONFIG_2__speed 2
#define O_MAC_CONFIG_2__hugen 5
#define O_MAC_CONFIG_2__flchk 4
#define O_MAC_CONFIG_2__crce 1
#define O_MAC_CONFIG_2__fulld 0
#define R_IPG_IFG 0x02
#define O_IPG_IFG__ipgr1 24
#define W_IPG_IFG__ipgr1 7
#define O_IPG_IFG__ipgr2 16
#define W_IPG_IFG__ipgr2 7
#define O_IPG_IFG__mifg 8
#define W_IPG_IFG__mifg 8
#define O_IPG_IFG__ipgt 0
#define W_IPG_IFG__ipgt 7
#define R_HALF_DUPLEX 0x03
#define O_HALF_DUPLEX__abebt 24
#define W_HALF_DUPLEX__abebt 4
#define O_HALF_DUPLEX__abebe 19
#define O_HALF_DUPLEX__bpnb 18
#define O_HALF_DUPLEX__nobo 17
#define O_HALF_DUPLEX__edxsdfr 16
#define O_HALF_DUPLEX__retry 12
#define W_HALF_DUPLEX__retry 4
#define O_HALF_DUPLEX__lcol 0
#define W_HALF_DUPLEX__lcol 10
#define R_MAXIMUM_FRAME_LENGTH 0x04
#define O_MAXIMUM_FRAME_LENGTH__maxf 0
#define W_MAXIMUM_FRAME_LENGTH__maxf 16
#define R_TEST 0x07
#define O_TEST__mbof 3
#define O_TEST__rthdf 2
#define O_TEST__tpause 1
#define O_TEST__sstct 0
#define R_MII_MGMT_CONFIG 0x08
#define O_MII_MGMT_CONFIG__scinc 5
#define O_MII_MGMT_CONFIG__spre 4
#define O_MII_MGMT_CONFIG__clks 3
#define W_MII_MGMT_CONFIG__clks 3
#define R_MII_MGMT_COMMAND 0x09
#define O_MII_MGMT_COMMAND__scan 1
#define O_MII_MGMT_COMMAND__rstat 0
#define R_MII_MGMT_ADDRESS 0x0A
#define O_MII_MGMT_ADDRESS__fiad 8
#define W_MII_MGMT_ADDRESS__fiad 5
#define O_MII_MGMT_ADDRESS__fgad 5
#define W_MII_MGMT_ADDRESS__fgad 0
#define R_MII_MGMT_WRITE_DATA 0x0B
#define O_MII_MGMT_WRITE_DATA__ctld 0
#define W_MII_MGMT_WRITE_DATA__ctld 16
#define R_MII_MGMT_STATUS 0x0C
#define R_MII_MGMT_INDICATORS 0x0D
#define O_MII_MGMT_INDICATORS__nvalid 2
#define O_MII_MGMT_INDICATORS__scan 1
#define O_MII_MGMT_INDICATORS__busy 0
#define R_INTERFACE_CONTROL 0x0E
#define O_INTERFACE_CONTROL__hrstint 31
#define O_INTERFACE_CONTROL__tbimode 27
#define O_INTERFACE_CONTROL__ghdmode 26
#define O_INTERFACE_CONTROL__lhdmode 25
#define O_INTERFACE_CONTROL__phymod 24
#define O_INTERFACE_CONTROL__hrrmi 23
#define O_INTERFACE_CONTROL__rspd 16
#define O_INTERFACE_CONTROL__hr100 15
#define O_INTERFACE_CONTROL__frcq 10
#define O_INTERFACE_CONTROL__nocfr 9
#define O_INTERFACE_CONTROL__dlfct 8
#define O_INTERFACE_CONTROL__enjab 0
#define R_INTERFACE_STATUS 0x0F
#define O_INTERFACE_STATUS__xsdfr 9
#define O_INTERFACE_STATUS__ssrr 8
#define W_INTERFACE_STATUS__ssrr 5
#define O_INTERFACE_STATUS__miilf 3
#define O_INTERFACE_STATUS__locar 2
#define O_INTERFACE_STATUS__sqerr 1
#define O_INTERFACE_STATUS__jabber 0
#define R_STATION_ADDRESS_LS 0x10
#define R_STATION_ADDRESS_MS 0x11
/* A-XGMAC register and bit field definitions */
#define R_XGMAC_CONFIG_0 0x00
#define O_XGMAC_CONFIG_0__hstmacrst 31
#define O_XGMAC_CONFIG_0__hstrstrctl 23
#define O_XGMAC_CONFIG_0__hstrstrfn 22
#define O_XGMAC_CONFIG_0__hstrsttctl 18
#define O_XGMAC_CONFIG_0__hstrsttfn 17
#define O_XGMAC_CONFIG_0__hstrstmiim 16
#define O_XGMAC_CONFIG_0__hstloopback 8
#define R_XGMAC_CONFIG_1 0x01
#define O_XGMAC_CONFIG_1__hsttctlen 31
#define O_XGMAC_CONFIG_1__hsttfen 30
#define O_XGMAC_CONFIG_1__hstrctlen 29
#define O_XGMAC_CONFIG_1__hstrfen 28
#define O_XGMAC_CONFIG_1__tfen 26
#define O_XGMAC_CONFIG_1__rfen 24
#define O_XGMAC_CONFIG_1__hstrctlshrtp 12
#define O_XGMAC_CONFIG_1__hstdlyfcstx 10
#define W_XGMAC_CONFIG_1__hstdlyfcstx 2
#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8
#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2
#define O_XGMAC_CONFIG_1__hstppen 7
#define O_XGMAC_CONFIG_1__hstbytswp 6
#define O_XGMAC_CONFIG_1__hstdrplt64 5
#define O_XGMAC_CONFIG_1__hstprmscrx 4
#define O_XGMAC_CONFIG_1__hstlenchk 3
#define O_XGMAC_CONFIG_1__hstgenfcs 2
#define O_XGMAC_CONFIG_1__hstpadmode 0
#define W_XGMAC_CONFIG_1__hstpadmode 2
#define R_XGMAC_CONFIG_2 0x02
#define O_XGMAC_CONFIG_2__hsttctlfrcp 31
#define O_XGMAC_CONFIG_2__hstmlnkflth 27
#define O_XGMAC_CONFIG_2__hstalnkflth 26
#define O_XGMAC_CONFIG_2__rflnkflt 24
#define W_XGMAC_CONFIG_2__rflnkflt 2
#define O_XGMAC_CONFIG_2__hstipgextmod 16
#define W_XGMAC_CONFIG_2__hstipgextmod 5
#define O_XGMAC_CONFIG_2__hstrctlfrcp 15
#define O_XGMAC_CONFIG_2__hstipgexten 5
#define O_XGMAC_CONFIG_2__hstmipgext 0
#define W_XGMAC_CONFIG_2__hstmipgext 5
#define R_XGMAC_CONFIG_3 0x03
#define O_XGMAC_CONFIG_3__hstfltrfrm 31
#define W_XGMAC_CONFIG_3__hstfltrfrm 16
#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15
#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16
#define R_XGMAC_STATION_ADDRESS_LS 0x04
#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0
#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32
#define R_XGMAC_STATION_ADDRESS_MS 0x05
#define R_XGMAC_MAX_FRAME_LEN 0x08
#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16
#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14
#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0
#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16
#define R_XGMAC_REV_LEVEL 0x0B
#define O_XGMAC_REV_LEVEL__revlvl 0
#define W_XGMAC_REV_LEVEL__revlvl 15
#define R_XGMAC_MIIM_COMMAND 0x10
#define O_XGMAC_MIIM_COMMAND__hstldcmd 3
#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0
#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3
#define R_XGMAC_MIIM_FILED 0x11
#define O_XGMAC_MIIM_FILED__hststfield 30
#define W_XGMAC_MIIM_FILED__hststfield 2
#define O_XGMAC_MIIM_FILED__hstopfield 28
#define W_XGMAC_MIIM_FILED__hstopfield 2
#define O_XGMAC_MIIM_FILED__hstphyadx 23
#define W_XGMAC_MIIM_FILED__hstphyadx 5
#define O_XGMAC_MIIM_FILED__hstregadx 18
#define W_XGMAC_MIIM_FILED__hstregadx 5
#define O_XGMAC_MIIM_FILED__hsttafield 16
#define W_XGMAC_MIIM_FILED__hsttafield 2
#define O_XGMAC_MIIM_FILED__miimrddat 0
#define W_XGMAC_MIIM_FILED__miimrddat 16
#define R_XGMAC_MIIM_CONFIG 0x12
#define O_XGMAC_MIIM_CONFIG__hstnopram 7
#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0
#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7
#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13
#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0
#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32
#define R_XGMAC_MIIM_INDICATOR 0x14
#define O_XGMAC_MIIM_INDICATOR__miimphylf 4
#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3
#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2
#define O_XGMAC_MIIM_INDICATOR__miimmon 1
#define O_XGMAC_MIIM_INDICATOR__miimbusy 0
/* GMAC stats registers */
#define R_RBYT 0x27
#define R_RPKT 0x28
#define R_RFCS 0x29
#define R_RMCA 0x2A
#define R_RBCA 0x2B
#define R_RXCF 0x2C
#define R_RXPF 0x2D
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