// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2012 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Contributors:
* Manjunath Hadli <manjunath.hadli@ti.com>
* Prabhakar Lad <prabhakar.lad@ti.com>
*/
#include "dm365_ipipe_hw.h"
#define IPIPE_MODE_CONTINUOUS 0
#define IPIPE_MODE_SINGLE_SHOT 1
static void ipipe_clock_enable(void __iomem *base_addr)
{
/* enable IPIPE MMR for register write access */
regw_ip(base_addr, IPIPE_GCK_MMR_DEFAULT, IPIPE_GCK_MMR);
/* enable the clock wb,cfa,dfc,d2f,pre modules */
regw_ip(base_addr, IPIPE_GCK_PIX_DEFAULT, IPIPE_GCK_PIX);
}
static void
rsz_set_common_params(void __iomem *rsz_base, struct resizer_params *params)
{
struct rsz_common_params *rsz_common = ¶ms->rsz_common;
u32 val;
/* Set mode */
regw_rsz(rsz_base, params->oper_mode, RSZ_SRC_MODE);
/* data source selection and bypass */
val = (rsz_common->passthrough << RSZ_BYPASS_SHIFT) |
rsz_common->source;
regw_rsz(rsz_base, val, RSZ_SRC_FMT0);
/* src image selection */
val = (rsz_common->raw_flip & 1) |
(rsz_common->src_img_fmt << RSZ_SRC_IMG_FMT_SHIFT) |
((rsz_common->y_c & 1) << RSZ_SRC_Y_C_SEL_SHIFT);
regw_rsz(rsz_base, val, RSZ_SRC_FMT1);
regw_rsz(rsz_base, rsz_common->vps & IPIPE_RSZ_VPS_MASK, RSZ_SRC_VPS);
regw_rsz(rsz_base, rsz_common->hps & IPIPE_RSZ_HPS_MASK, RSZ_SRC_HPS);
regw_rsz(rsz_base, rsz_common->vsz & IPIPE_RSZ_VSZ_MASK, RSZ_SRC_VSZ);
regw_rsz(rsz_base, rsz_common->hsz & IPIPE_RSZ_HSZ_MASK, RSZ_SRC_HSZ);
regw_rsz(rsz_base, rsz_common->yuv_y_min, RSZ_YUV_Y_MIN);
regw_rsz(rsz_base, rsz_common->yuv_y_max, RSZ_YUV_Y_MAX);
regw_rsz(rsz_base, rsz_common->yuv_c_min, RSZ_YUV_C_MIN);
regw_rsz(rsz_base, rsz_common->yuv_c_max, RSZ_YUV_C_MAX);
/* chromatic position */
regw_rsz(rsz_base, rsz_common->out_chr_pos, RSZ_YUV_PHS);
}
static void
rsz_set_rsz_regs(void __iomem *rsz_base, unsigned int rsz_id,
struct resizer_params *params)
{
struct resizer_scale_param *rsc_params;
struct rsz_ext_mem_param *ext_mem;
struct resizer_rgb *rgb;
u32 reg_base;
u32 val;
rsc_params = ¶ms->rsz_rsc_param[rsz_id];
rgb = ¶ms->rsz2rgb[rsz_id];
ext_mem = ¶ms->ext_mem_param[rsz_id];
if (rsz_id == RSZ_A) {
val = rsc_params->h_flip << RSZA_H_FLIP_SHIFT;
val |= rsc_params->v_flip << RSZA_V_FLIP_SHIFT;
reg_base = RSZ_EN_A;
} else {
val = rsc_params->h_flip << RSZB_H_FLIP_SHIFT;
val |= rsc_params->v_flip << RSZB_V_FLIP_SHIFT;
reg_base = RSZ_EN_B;
}
/* update flip settings */
regw_rsz(rsz_base, val, RSZ_SEQ);
regw_rsz(rsz_base, params->oper_mode, reg_base + RSZ_MODE);
val = (rsc_params->cen << RSZ_CEN_SHIFT) | rsc_params->yen;
regw_rsz(rsz_base, val, reg_base + RSZ_420);
regw_rsz(rsz_base, rsc_params->i_vps & RSZ_VPS_MASK,
reg_base + RSZ_I_VPS);
regw_rsz(rsz_base, rsc_params->i_hps & RSZ_HPS_MASK,
reg_base + RSZ_I_HPS);
regw_rsz(rsz_base, rsc_params->o_vsz & RSZ_O_VSZ_MASK,
reg_base + RSZ_O_VSZ);
regw_rsz(rsz_base, rsc_params->o_hsz & RSZ_O_HSZ_MASK,
reg_base + RSZ_O_HSZ);
regw_rsz(rsz_base, rsc_params->v_phs_y & RSZ_V_PHS_MASK,
reg_base + RSZ_V_PHS_Y);
regw_rsz(rsz_base, rsc_params->v_phs_c & RSZ_V_PHS_MASK,
reg_base + RSZ_V_PHS_C);
/* keep this additional adjustment to zero for now */
regw_rsz(rsz_base, rsc_params->v_dif & RSZ_V_DIF_MASK,
reg_base + RSZ_V_DIF);