path: root/drivers/staging/comedi/drivers/quatech_daqp_cs.c

/*
 * quatech_daqp_cs.c
 * Quatech DAQP PCMCIA data capture cards COMEDI client driver
 * Copyright (C) 2000, 2003 Brent Baccala <baccala@freesoft.org>
 * The DAQP interface code in this file is released into the public domain.
 *
 * COMEDI - Linux Control and Measurement Device Interface
 * Copyright (C) 1998 David A. Schleef <ds@schleef.org>
 * http://www.comedi.org/
 *
 * Documentation for the DAQP PCMCIA cards can be found on Quatech's site:
 *	ftp://ftp.quatech.com/Manuals/daqp-208.pdf
 *
 * This manual is for both the DAQP-208 and the DAQP-308.
 *
 * What works:
 * - A/D conversion
 *	- 8 channels
 *	- 4 gain ranges
 *	- ground ref or differential
 *	- single-shot and timed both supported
 * - D/A conversion, single-shot
 * - digital I/O
 *
 * What doesn't:
 * - any kind of triggering - external or D/A channel 1
 * - the card's optional expansion board
 * - the card's timer (for anything other than A/D conversion)
 * - D/A update modes other than immediate (i.e, timed)
 * - fancier timing modes
 * - setting card's FIFO buffer thresholds to anything but default
 */

/*
 * Driver: quatech_daqp_cs
 * Description: Quatech DAQP PCMCIA data capture cards
 * Devices: [Quatech] DAQP-208 (daqp), DAQP-308
 * Author: Brent Baccala <baccala@freesoft.org>
 * Status: works
 */

#include <linux/module.h>

#include "../comedi_pcmcia.h"

/*
 * Register I/O map
 *
 * The D/A and timer registers can be accessed with 16-bit or 8-bit I/O
 * instructions. All other registers can only use 8-bit instructions.
 *
 * The FIFO and scanlist registers require two 8-bit instructions to
 * access the 16-bit data. Data is transferred LSB then MSB.
 */
#define DAQP_AI_FIFO_REG		0x00

#define DAQP_SCANLIST_REG		0x01
#define DAQP_SCANLIST_DIFFERENTIAL	BIT(14)
#define DAQP_SCANLIST_GAIN(x)		(((x) & 0x3) << 12)
#define DAQP_SCANLIST_CHANNEL(x)	(((x) & 0xf) << 8)
#define DAQP_SCANLIST_START		BIT(7)
#define DAQP_SCANLIST_EXT_GAIN(x)	(((x) & 0x3) << 4)
#define DAQP_SCANLIST_EXT_CHANNEL(x)	(((x) & 0xf) << 0)

#define DAQP_CTRL_REG			0x02
#define DAQP_CTRL_PACER_CLK(x)		(((x) & 0x3) << 6)
#define DAQP_CTRL_PACER_CLK_EXT		DAQP_CTRL_PACER_CLK(0)
#define DAQP_CTRL_PACER_CLK_5MHZ	DAQP_CTRL_PACER_CLK(1)
#define DAQP_CTRL_PACER_CLK_1MHZ	DAQP_CTRL_PACER_CLK(2)
#define DAQP_CTRL_PACER_CLK_100KHZ	DAQP_CTRL_PACER_CLK(3)
#define DAQP_CTRL_EXPANSION		BIT(5)
#define DAQP_CTRL_EOS_INT_ENA		BIT(4)
#define DAQP_CTRL_FIFO_INT_ENA		BIT(3)
#define DAQP_CTRL_TRIG_MODE		BIT(2)	/* 0=one-shot; 1=continuous */
#define DAQP_CTRL_TRIG_SRC		BIT(1)	/* 0=internal; 1=external */
#define DAQP_CTRL_TRIG_EDGE		BIT(0)	/* 0=rising; 1=falling */

#define DAQP_STATUS_REG			0x02
#define DAQP_STATUS_IDLE		BIT(7)
#define DAQP_STATUS_RUNNING		BIT(6)
#define DAQP_STATUS_DATA_LOST		BIT(5)
#define DAQP_STATUS_END_OF_SCAN		BIT(4)
#define DAQP_STATUS_FIFO_THRESHOLD	BIT(3)
#define DAQP_STATUS_FIFO_FULL		BIT(2)
#define DAQP_STATUS_FIFO_NEARFULL	BIT(1)
#define DAQP_STATUS_FIFO_EMPTY		BIT(0)
/* these bits clear when the status register is read */
#define DAQP_STATUS_EVENTS		(DAQP_STATUS_DATA_LOST |	\
					 DAQP_STATUS_END_OF_SCAN |	\
					 DAQP_STATUS_FIFO_THRESHOLD)

#define DAQP_DI_REG			0x03
#define DAQP_DO_REG			0x03

#define DAQP_PACER_LOW_REG		0x04
#define DAQP_PACER_MID_REG		0x05
#define DAQP_PACER_HIGH_REG		0x06

#define DAQP_CMD_REG			0x07
/* the monostable bits are self-clearing after the function is complete */
#define DAQP_CMD_ARM			BIT(7)	/* monostable */
#define DAQP_CMD_RSTF			BIT(6)	/* monostable */
#define DAQP_CMD_RSTQ			BIT(5)	/* monostable */
#define DAQP_CMD_STOP			BIT(4)	/* monostable */
#define DAQP_CMD_LATCH			BIT(3)	/* monostable */
#define DAQP_CMD_SCANRATE(x)		(((x) & 0x3) << 1)
#define DAQP_CMD_SCANRATE_100KHZ	DAQP_CMD_SCANRATE(0)
#define DAQP_CMD_SCANRATE_50KHZ		DAQP_CMD_SCANRATE(1)
#define DAQP_CMD_SCANRATE_25KHZ		DAQP_CMD_SCANRATE(2)
#define DAQP_CMD_FIFO_DATA		BIT(0)

#define DAQP_AO_REG			0x08	/* and 0x09 (16-bit) */

#define DAQP_TIMER_REG			0x0a	/* and 0x0b (16-bit) */

#define DAQP_AUX_REG			0x0f
/* Auxiliary Control register bits (write) */
#define DAQP_AUX_EXT_ANALOG_TRIG	BIT(7)
#define DAQP_AUX_PRETRIG		BIT(6)
#define DAQP_AUX_TIMER_INT_ENA		BIT(5)
#define DAQP_AUX_TIMER_MODE(x)		(((x) & 0x3) << 3)
#define DAQP_AUX_TIMER_MODE_RELOAD	DAQP_AUX_TIMER_MODE(0)
#define DAQP_AUX_TIMER_MODE_PAUSE	DAQP_AUX_TIMER_MODE(1)
#define DAQP_AUX_TIMER_MODE_GO		DAQP_AUX_TIMER_MODE(2)
#define DAQP_AUX_TIMER_MODE_EXT		DAQP_AUX_TIMER_MODE(3)
#define DAQP_AUX_TIMER_CLK_SRC_EXT	BIT(2)
#define DAQP_AUX_DA_UPDATE(x)		(((x) & 0x3) << 0)
#define DAQP_AUX_DA_UPDATE_DIRECT	DAQP_AUX_DA_UPDATE(0)
#define DAQP_AUX_DA_UPDATE_OVERFLOW	DAQP_AUX_DA_UPDATE(1)
#define DAQP_AUX_DA_UPDATE_EXTERNAL	DAQP_AUX_DA_UPDATE(2)
#define DAQP_AUX_DA_UPDATE_PACER	DAQP_AUX_DA_UPDATE(3)
/* Auxiliary Status register bits (read) */
#define DAQP_AUX_RUNNING		BIT(7)
#define DAQP_AUX_TRIGGERED		BIT(6)
#define DAQP_AUX_DA_BUFFER		BIT(5)
#define DAQP_AUX_TIMER_OVERFLOW		BIT(4)
#define DAQP_AUX_CONVERSION		BIT(3)
#define DAQP_AUX_DATA_LOST		BIT(2)
#define DAQP_AUX_FIFO_NEARFULL		BIT(1)
#define DAQP_AUX_FIFO_EMPTY		BIT(0)

#define DAQP_FIFO_SIZE			4096

#define DAQP_MAX_TIMER_SPEED		10000	/* 100 kHz in nanoseconds */

struct daqp_private {
	unsigned int pacer_div;
	int stop;
};

static const struct comedi_lrange range_daqp_ai = {
	4, {
		BIP_RANGE(10),
		BIP_RANGE(5),
		BIP_RANGE(2.5),
		BIP_RANGE(1.25)
	}
};

static int daqp_clear_events(struct comedi_device *dev, int loops)
{
	unsigned int status;

	/*
	 * Reset any pending interrupts (my card has a tendency to require
	 * require multiple reads on the status register to achieve this).
	 */
	while (--loops) {
		status = inb(dev->iobase + DAQP_STATUS_REG);
		if ((status & DAQP_STATUS_EVENTS) == 0)
			return 0;
	}
	dev_err(dev->class_dev, "couldn't clear events in status register\n");
	return -EBUSY;
}

static int daqp_ai_cancel(struct comedi_device *dev,
			  struct comedi_subdevice *s)
{
	struct daqp_private *devpriv = dev->private;

	if (devpriv->stop)
		return -EIO;

	/*
	 * Stop any conversions, disable interrupts, and clear
	 * the status event flags.
	 */
	outb(DAQP_CMD_STOP, dev->iobase + DAQP_CMD_REG);
	outb(0, dev->iobase + DAQP_CTRL_REG);
	inb(dev->iobase + DAQP_STATUS_REG);

	return 0;
}

static unsigned int daqp_ai_get_sample(struct comedi_device *dev,
				       struct comedi_subdevice *s)
{
	unsigned int val;

	/*
	 * Get a two's complement sample from the FIFO and
	 * return the munged offset binary value.
	 */
	val = inb(dev->iobase + DAQP_AI_FIFO_REG);
	val |= inb(dev->iobase + DAQP_AI_FIFO_REG) << 8;
	return comedi_offset_munge(s, val);
}

static irqreturn_t daqp_interrupt(int irq, void *dev_id)
{
	struct comedi_device *dev = dev_id;
	struct comedi_subdevice *s = dev->read_subdev;
	struct comedi_cmd *cmd = &s->async->cmd;
	int loop_limit = 10000;
	int status;

	if (!dev->attached)
		return IRQ_NONE;

	status = inb(dev->iobase + DAQP_STATUS_REG);
	if (!(status & DAQP_STATUS_EVENTS))
		return IRQ_NONE;

	while (!(status & DAQP_STATUS_FIFO_EMPTY)) {
		unsigned short data;

		if (status & DAQP_STATUS_DATA_LOST) {
			s->async->events |= COMEDI_CB_OVERFLOW;
			dev_warn(dev->class_dev, "data lost\n");
			break;
		}

		data = daqp_ai_get_sample(dev, s);
		comedi_buf_write_samples(s, &data, 1);

		if (cmd->stop_src == TRIG_COUNT &&
		    s->async->scans_done >= cmd->stop_arg) {
			s->async->events |= COMEDI_CB_EOA;
			break;
		}

		if ((loop_limit--) <= 0)
			break;

		status = inb(dev->iobase + DAQP_STATUS_REG);
	}

	if (loop_limit <= 0) {
		dev_warn(dev->class_dev,
			 "loop_limit reached in %s()\n", __func__);
		s->async->events |= COMEDI_CB_ERROR;
	}

	comedi_handle_events(dev, s);

	return IRQ_HANDLED;
}

static void daqp_ai_set_one_scanlist_entry(struct comedi_device *dev,
					   unsigned int chanspec,
					   int start)
{
	unsigned int chan = CR_CHAN