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|
// SPDX-License-Identifier: GPL-2.0+
/*
* addi_apci_1564.c
* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
*
* ADDI-DATA GmbH
* Dieselstrasse 3
* D-77833 Ottersweier
* Tel: +19(0)7223/9493-0
* Fax: +49(0)7223/9493-92
* http://www.addi-data.com
* info@addi-data.com
*/
/*
* Driver: addi_apci_1564
* Description: ADDI-DATA APCI-1564 Digital I/O board
* Devices: [ADDI-DATA] APCI-1564 (addi_apci_1564)
* Author: H Hartley Sweeten <hsweeten@visionengravers.com>
* Updated: Thu, 02 Jun 2016 13:12:46 -0700
* Status: untested
*
* Configuration Options: not applicable, uses comedi PCI auto config
*
* This board has the following features:
* - 32 optically isolated digital inputs (24V), 16 of which can
* generate change-of-state (COS) interrupts (channels 4 to 19)
* - 32 optically isolated digital outputs (10V to 36V)
* - 1 8-bit watchdog for resetting the outputs
* - 1 12-bit timer
* - 3 32-bit counters
* - 2 diagnostic inputs
*
* The COS, timer, and counter subdevices all use the dev->read_subdev to
* return the interrupt status. The sample data is updated and returned when
* any of these subdevices generate an interrupt. The sample data format is:
*
* Bit Description
* ----- ------------------------------------------
* 31 COS interrupt
* 30 timer interrupt
* 29 counter 2 interrupt
* 28 counter 1 interrupt
* 27 counter 0 interrupt
* 26:20 not used
* 19:4 COS digital input state (channels 19 to 4)
* 3:0 not used
*
* The COS interrupts must be configured using an INSN_CONFIG_DIGITAL_TRIG
* instruction before they can be enabled by an async command. The COS
* interrupts will stay active until canceled.
*
* The timer subdevice does not use an async command. All control is handled
* by the (*insn_config).
*
* FIXME: The format of the ADDI_TCW_TIMEBASE_REG is not descibed in the
* datasheet I have. The INSN_CONFIG_SET_CLOCK_SRC currently just writes
* the raw data[1] to this register along with the raw data[2] value to the
* ADDI_TCW_RELOAD_REG. If anyone tests this and can determine the actual
* timebase/reload operation please let me know.
*
* The counter subdevice also does not use an async command. All control is
* handled by the (*insn_config).
*
* FIXME: The operation of the counters is not really described in the
* datasheet I have. The (*insn_config) needs more work.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include "../comedi_pci.h"
#include "addi_tcw.h"
#include "addi_watchdog.h"
/*
* PCI BAR 0
*
* PLD Revision 1.0 I/O Mapping
* 0x00 93C76 EEPROM
* 0x04 - 0x18 Timer 12-Bit
*
* PLD Revision 2.x I/O Mapping
* 0x00 93C76 EEPROM
* 0x04 - 0x14 Digital Input
* 0x18 - 0x25 Digital Output
* 0x28 - 0x44 Watchdog 8-Bit
* 0x48 - 0x64 Timer 12-Bit
*/
#define APCI1564_EEPROM_REG 0x00
#define APCI1564_EEPROM_VCC_STATUS BIT(8)
#define APCI1564_EEPROM_TO_REV(x) (((x) >> 4) & 0xf)
#define APCI1564_EEPROM_DI BIT(3)
#define APCI1564_EEPROM_DO BIT(2)
#define APCI1564_EEPROM_CS BIT(1)
#define APCI1564_EEPROM_CLK BIT(0)
#define APCI1564_REV1_TIMER_IOBASE 0x04
#define APCI1564_REV2_MAIN_IOBASE 0x04
#define APCI1564_REV2_TIMER_IOBASE 0x48
/*
* PCI BAR 1
*
* PLD Revision 1.0 I/O Mapping
* 0x00 - 0x10 Digital Input
* 0x14 - 0x20 Digital Output
* 0x24 - 0x3c Watchdog 8-Bit
*
* PLD Revision 2.x I/O Mapping
* 0x00 Counter_0
* 0x20 Counter_1
* 0x30 Counter_3
*/
#define APCI1564_REV1_MAIN_IOBASE 0x00
/*
* dev->iobase Register Map
* PLD Revision 1.0 - PCI BAR 1 + 0x00
* PLD Revision 2.x - PCI BAR 0 + 0x04
*/
#define APCI1564_DI_REG 0x00
#define APCI1564_DI_INT_MODE1_REG 0x04
#define APCI1564_DI_INT_MODE2_REG 0x08
#define APCI1564_DI_INT_MODE_MASK 0x000ffff0 /* chans [19:4] */
#define APCI1564_DI_INT_STATUS_REG 0x0c
#define APCI1564_DI_IRQ_REG 0x10
#define APCI1564_DI_IRQ_ENA BIT(2)
#define APCI1564_DI_IRQ_MODE BIT(1) /* 1=AND, 0=OR */
#define APCI1564_DO_REG 0x14
#define APCI1564_DO_INT_CTRL_REG 0x18
#define APCI1564_DO_INT_CTRL_CC_INT_ENA BIT(1)
#define APCI1564_DO_INT_CTRL_VCC_INT_ENA BIT(0)
#define APCI1564_DO_INT_STATUS_REG 0x1c
#define APCI1564_DO_INT_STATUS_CC BIT(1)
#define APCI1564_DO_INT_STATUS_VCC BIT(0)
#define APCI1564_DO_IRQ_REG 0x20
#define APCI1564_DO_IRQ_INTR BIT(0)
#define APCI1564_WDOG_IOBASE 0x24
/*
* devpriv->timer Register Map (see addi_tcw.h for register/bit defines)
* PLD Revision 1.0 - PCI BAR 0 + 0x04
* PLD Revision 2.x - PCI BAR 0 + 0x48
*/
/*
* devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
* PLD Revision 2.x - PCI BAR 1 + 0x00
*/
#define APCI1564_COUNTER(x) ((x) * 0x20)
/*
* The dev->read_subdev is used to return the interrupt events along with
* the state of the interrupt capable inputs.
*/
#define APCI1564_EVENT_COS BIT(31)
#define APCI1564_EVENT_TIMER BIT(30)
#define APCI1564_EVENT_COUNTER(x) BIT(27 + (x)) /* counter 0-2 */
#define APCI1564_EVENT_MASK 0xfff0000f /* all but [19:4] */
struct apci1564_private {
unsigned long eeprom; /* base address of EEPROM register */
unsigned long timer; /* base address of 12-bit timer */
unsigned long counters; /* base address of 32-bit counters */
unsigned int mode1; /* rising-edge/high level channels */
unsigned int mode2; /* falling-edge/low level channels */
unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
};
static int apci1564_reset(struct comedi_device *dev)
{
struct apci1564_private *devpriv = dev->private;
/* Disable the input interrupts and reset status register */
outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
/* Reset the output channels and disable interrupts */
outl(0x0, dev->iobase + APCI1564_DO_REG);
outl(0x0, dev->iobase + APCI1564_DO_INT_CTRL_REG);
/* Reset the watchdog registers */
addi_watchdog_reset(dev->iobase + APCI1564_WDOG_IOBASE);
/* Reset the timer registers */
outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
if (devpriv->counters) {
unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
/* Reset the counter registers */
outl(0x0, iobase + APCI1564_COUNTER(0));
outl(0x0, iobase + APCI1564_COUNTER(1));
outl(0x0, iobase + APCI1564_COUNTER(2));
}
return 0;
}
static irqreturn_t apci1564_interrupt(int irq, void *d)
{
struct comedi_device *dev = d;
struct apci1564_private *devpriv = dev->private;
struct comedi_subdevice *s = dev->read_subdev;
unsigned int status;
unsigned int ctrl;
unsigned int chan;
s->state &= ~APCI1564_EVENT_MASK;
status = inl(dev->iobase + APCI1564_DI_IRQ_REG);
if (status & APCI1564_DI_IRQ_ENA) {
/* get the COS interrupt state and set the event flag */
s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
s->state &= APCI1564_DI_INT_MODE_MASK;
s->state |= APCI1564_EVENT_COS;
/* clear the interrupt */
outl(status & ~APCI1564_DI_IRQ_ENA,
dev->iobase + APCI1564_DI_IRQ_REG);
outl(status, dev->iobase + APCI1564_DI_IRQ_REG);
}
status = inl(devpriv->timer + ADDI_TCW_IRQ_REG);
if (status & ADDI_TCW_IRQ) {
s->state |= APCI1564_EVENT_TIMER;
/* clear the interrupt */
ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
}
if (devpriv->counters) {
for (chan = 0; chan < 3; chan++) {
unsigned long iobase;
iobase = devpriv->counters + APCI1564_COUNTER(chan);
status = inl(iobase + ADDI_TCW_IRQ_REG);
if (status & ADDI_TCW_IRQ) {
s->state |= APCI1564_EVENT_COUNTER(chan);
/* clear the interrupt */
ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
outl(0x0, iobase + ADDI_TCW_CTRL_REG);
outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
}
}
}
if (s->state & APCI1564_EVENT_MASK
|