path: root/drivers/spi/spi-lantiq-ssc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>

#ifdef CONFIG_LANTIQ
#include <lantiq_soc.h>
#endif

#define LTQ_SPI_RX_IRQ_NAME	"spi_rx"
#define LTQ_SPI_TX_IRQ_NAME	"spi_tx"
#define LTQ_SPI_ERR_IRQ_NAME	"spi_err"
#define LTQ_SPI_FRM_IRQ_NAME	"spi_frm"

#define LTQ_SPI_CLC		0x00
#define LTQ_SPI_PISEL		0x04
#define LTQ_SPI_ID		0x08
#define LTQ_SPI_CON		0x10
#define LTQ_SPI_STAT		0x14
#define LTQ_SPI_WHBSTATE	0x18
#define LTQ_SPI_TB		0x20
#define LTQ_SPI_RB		0x24
#define LTQ_SPI_RXFCON		0x30
#define LTQ_SPI_TXFCON		0x34
#define LTQ_SPI_FSTAT		0x38
#define LTQ_SPI_BRT		0x40
#define LTQ_SPI_BRSTAT		0x44
#define LTQ_SPI_SFCON		0x60
#define LTQ_SPI_SFSTAT		0x64
#define LTQ_SPI_GPOCON		0x70
#define LTQ_SPI_GPOSTAT		0x74
#define LTQ_SPI_FPGO		0x78
#define LTQ_SPI_RXREQ		0x80
#define LTQ_SPI_RXCNT		0x84
#define LTQ_SPI_DMACON		0xec
#define LTQ_SPI_IRNEN		0xf4

#define LTQ_SPI_CLC_SMC_S	16	/* Clock divider for sleep mode */
#define LTQ_SPI_CLC_SMC_M	(0xFF << LTQ_SPI_CLC_SMC_S)
#define LTQ_SPI_CLC_RMC_S	8	/* Clock divider for normal run mode */
#define LTQ_SPI_CLC_RMC_M	(0xFF << LTQ_SPI_CLC_RMC_S)
#define LTQ_SPI_CLC_DISS	BIT(1)	/* Disable status bit */
#define LTQ_SPI_CLC_DISR	BIT(0)	/* Disable request bit */

#define LTQ_SPI_ID_TXFS_S	24	/* Implemented TX FIFO size */
#define LTQ_SPI_ID_RXFS_S	16	/* Implemented RX FIFO size */
#define LTQ_SPI_ID_MOD_S	8	/* Module ID */
#define LTQ_SPI_ID_MOD_M	(0xff << LTQ_SPI_ID_MOD_S)
#define LTQ_SPI_ID_CFG_S	5	/* DMA interface support */
#define LTQ_SPI_ID_CFG_M	(1 << LTQ_SPI_ID_CFG_S)
#define LTQ_SPI_ID_REV_M	0x1F	/* Hardware revision number */

#define LTQ_SPI_CON_BM_S	16	/* Data width selection */
#define LTQ_SPI_CON_BM_M	(0x1F << LTQ_SPI_CON_BM_S)
#define LTQ_SPI_CON_EM		BIT(24)	/* Echo mode */
#define LTQ_SPI_CON_IDLE	BIT(23)	/* Idle bit value */
#define LTQ_SPI_CON_ENBV	BIT(22)	/* Enable byte valid control */
#define LTQ_SPI_CON_RUEN	BIT(12)	/* Receive underflow error enable */
#define LTQ_SPI_CON_TUEN	BIT(11)	/* Transmit underflow error enable */
#define LTQ_SPI_CON_AEN		BIT(10)	/* Abort error enable */
#define LTQ_SPI_CON_REN		BIT(9)	/* Receive overflow error enable */
#define LTQ_SPI_CON_TEN		BIT(8)	/* Transmit overflow error enable */
#define LTQ_SPI_CON_LB		BIT(7)	/* Loopback control */
#define LTQ_SPI_CON_PO		BIT(6)	/* Clock polarity control */
#define LTQ_SPI_CON_PH		BIT(5)	/* Clock phase control */
#define LTQ_SPI_CON_HB		BIT(4)	/* Heading control */
#define LTQ_SPI_CON_RXOFF	BIT(1)	/* Switch receiver off */
#define LTQ_SPI_CON_TXOFF	BIT(0)	/* Switch transmitter off */

#define LTQ_SPI_STAT_RXBV_S	28
#define LTQ_SPI_STAT_RXBV_M	(0x7 << LTQ_SPI_STAT_RXBV_S)
#define LTQ_SPI_STAT_BSY	BIT(13)	/* Busy flag */
#define LTQ_SPI_STAT_RUE	BIT(12)	/* Receive underflow error flag */
#define LTQ_SPI_STAT_TUE	BIT(11)	/* Transmit underflow error flag */
#define LTQ_SPI_STAT_AE		BIT(10)	/* Abort error flag */
#define LTQ_SPI_STAT_RE		BIT(9)	/* Receive error flag */
#define LTQ_SPI_STAT_TE		BIT(8)	/* Transmit error flag */
#define LTQ_SPI_STAT_ME		BIT(7)	/* Mode error flag */
#define LTQ_SPI_STAT_MS		BIT(1)	/* Master/slave select bit */
#define LTQ_SPI_STAT_EN		BIT(0)	/* Enable bit */
#define LTQ_SPI_STAT_ERRORS	(LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
				 LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
				 LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE)

#define LTQ_SPI_WHBSTATE_SETTUE	BIT(15)	/* Set transmit underflow error flag */
#define LTQ_SPI_WHBSTATE_SETAE	BIT(14)	/* Set abort error flag */
#define LTQ_SPI_WHBSTATE_SETRE	BIT(13)	/* Set receive error flag */
#define LTQ_SPI_WHBSTATE_SETTE	BIT(12)	/* Set transmit error flag */
#define LTQ_SPI_WHBSTATE_CLRTUE	BIT(11)	/* Clear transmit underflow error flag */
#define LTQ_SPI_WHBSTATE_CLRAE	BIT(10)	/* Clear abort error flag */
#define LTQ_SPI_WHBSTATE_CLRRE	BIT(9)	/* Clear receive error flag */
#define LTQ_SPI_WHBSTATE_CLRTE	BIT(8)	/* Clear transmit error flag */
#define LTQ_SPI_WHBSTATE_SETME	BIT(7)	/* Set mode error flag */
#define LTQ_SPI_WHBSTATE_CLRME	BIT(6)	/* Clear mode error flag */
#define LTQ_SPI_WHBSTATE_SETRUE	BIT(5)	/* Set receive underflow error flag */
#define LTQ_SPI_WHBSTATE_CLRRUE	BIT(4)	/* Clear receive underflow error flag */
#define LTQ_SPI_WHBSTATE_SETMS	BIT(3)	/* Set master select bit */
#define LTQ_SPI_WHBSTATE_CLRMS	BIT(2)	/* Clear master select bit */
#define LTQ_SPI_WHBSTATE_SETEN	BIT(1)	/* Set enable bit (operational mode) */
#define LTQ_SPI_WHBSTATE_CLREN	BIT(0)	/* Clear enable bit (config mode */
#define LTQ_SPI_WHBSTATE_CLR_ERRORS	(LTQ_SPI_WHBSTATE_CLRRUE | \
					 LTQ_SPI_WHBSTATE_CLRME | \
					 LTQ_SPI_WHBSTATE_CLRTE | \
					 LTQ_SPI_WHBSTATE_CLRRE | \
					 LTQ_SPI_WHBSTATE_CLRAE | \
					 LTQ_SPI_WHBSTATE_CLRTUE)

#define LTQ_SPI_RXFCON_RXFITL_S	8	/* FIFO interrupt trigger level */
#define LTQ_SPI_RXFCON_RXFLU	BIT(1)	/* FIFO flush */
#define LTQ_SPI_RXFCON_RXFEN	BIT(0)	/* FIFO enable */

#define LTQ_SPI_TXFCON_TXFITL_S	8	/* FIFO interrupt trigger level */
#define LTQ_SPI_TXFCON_TXFLU	BIT(1)	/* FIFO flush */
#define LTQ_SPI_TXFCON_TXFEN	BIT(0)	/* FIFO enable */

#define LTQ_SPI_FSTAT_RXFFL_S	0
#define LTQ_SPI_FSTAT_TXFFL_S	8

#define LTQ_SPI_GPOCON_ISCSBN_S	8
#define LTQ_SPI_GPOCON_INVOUTN_S	0

#define LTQ_SPI_FGPO_SETOUTN_S	8
#define LTQ_SPI_FGPO_CLROUTN_S	0

#define LTQ_SPI_RXREQ_RXCNT_M	0xFFFF	/* Receive count value */
#define LTQ_SPI_RXCNT_TODO_M	0xFFFF	/* Recevie to-do value */

#define LTQ_SPI_IRNEN_TFI	BIT(4)	/* TX finished interrupt */
#define LTQ_SPI_IRNEN_F		BIT(3)	/* Frame end interrupt request */
#define LTQ_SPI_IRNEN_E		BIT(2)	/* Error end interrupt request */
#define LTQ_SPI_IRNEN_T_XWAY	BIT(1)	/* Transmit end interrupt request */
#define LTQ_SPI_IRNEN_R_XWAY	BIT(0)	/* Receive end interrupt request */
#define LTQ_SPI_IRNEN_R_XRX	BIT(1)	/* Transmit end interrupt request */
#define LTQ_SPI_IRNEN_T_XRX	BIT(0)	/* Receive end interrupt request */
#define LTQ_SPI_IRNEN_ALL	0x1F

struct lantiq_ssc_spi;

struct lantiq_ssc_hwcfg {
	int (*cfg_irq)(struct platform_device *pdev, struct lantiq_ssc_spi *spi);
	unsigned int	irnen_r;
	unsigned int	irnen_t;
	unsigned int	irncr;
	unsigned int	irnicr;
	bool		irq_ack;
	u32		fifo_size_mask;
};

struct lantiq_ssc_spi {
	struct spi_master		*master;
	struct device			*dev;
	void __iomem			*regbase;
	struct clk			*spi_clk;
	struct clk			*fpi_clk;
	const struct lantiq_ssc_hwcfg	*hwcfg;

	spinlock_t			lock;
	struct workqueue_struct		*wq;
	struct work_struct		work;

	const u8			*tx;
	u8				*rx;
	unsigned int			tx_todo;
	unsigned int			rx_todo;
	unsigned int			bits_per_word;
	unsigned int			speed_hz;
	unsigned int			tx_fifo_size;
	unsigned int			rx_fifo_size;
	unsigned int			base_cs;
	unsigned int			fdx_tx_level;
};

static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
{
	return __raw_readl(spi->regbase + reg);
}

static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
			      u32 reg)
{
	__raw_writel(val, spi->regbase + reg);
}

static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
			     u32 set, u32 reg)
{
	u32 val = __raw_readl(spi->regbase