/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Flora Fu, MediaTek
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
#define PWRAP_MT8135_BRIDGE_INT_EN 0x38
#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
/* macro for wrapper status */
#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
#define PWRAP_STATE_INIT_DONE0 (1 << 21)
/* macro for WACS FSM */
#define PWRAP_WACS_FSM_IDLE 0x00
#define PWRAP_WACS_FSM_REQ 0x02
#define PWRAP_WACS_FSM_WFDLE 0x04
#define PWRAP_WACS_FSM_WFVLDCLR 0x06
#define PWRAP_WACS_INIT_DONE 0x01
#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
#define PWRAP_WACS_SYNC_BUSY 0x00
/* macro for device wrapper default value */
#define PWRAP_DEW_READ_TEST_VAL 0x5aa5
#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
/* macro for manual command */
#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
#define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
#define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
/* macro for Watch Dog Timer Source */
#define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
#define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
#define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
#define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
#define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
/* defines for slave device wrapper registers */
enum dew_regs {
PWRAP_DEW_BASE,
PWRAP_DEW_DIO_EN,
PWRAP_DEW_READ_TEST,
PWRAP_DEW_WRITE_TEST,
PWRAP_DEW_CRC_EN,
PWRAP_DEW_CRC_VAL,
PWRAP_DEW_MON_GRP_SEL,
PWRAP_DEW_CIPHER_KEY_SEL,
PWRAP_DEW_CIPHER_IV_SEL,
PWRAP_DEW_CIPHER_RDY,
PWRAP_DEW_CIPHER_MODE,
PWRAP_DEW_CIPHER_SWRST,
/* MT6397 only regs */
PWRAP_DEW_EVENT_OUT_EN,
PWRAP_DEW_EVENT_SRC_EN,
PWRAP_DEW_EVENT_SRC,
PWRAP_DEW_EVENT_FLAG,
PWRAP_DEW_MON_FLAG_SEL,
PWRAP_DEW_EVENT_TEST,
PWRAP_DEW_CIPHER_LOAD,
PWRAP_DEW_CIPHER_START,
/* MT6323 only regs */
PWRAP_DEW_CIPHER_EN,
PWRAP_DEW_RDDMY_NO,
};
static const u32 mt6323_regs[] = {
[PWRAP_DEW_BASE] = 0x0000,
[PWRAP_DEW_DIO_EN] = 0x018a,
[PWRAP_DEW_READ_TEST] = 0x018c,
[PWRAP_DEW_WRITE_TEST] = 0x018e,
[PWRAP_DEW_CRC_EN] = 0x0192,
[PWRAP_DEW_CRC_VAL] = 0x0194,
[PWRAP_DEW_MON_GRP_SEL] = 0x0196,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
[PWRAP_DEW_CIPHER_EN] = 0x019c,
[PWRAP_DEW_CIPHER_RDY] = 0x019e,
[PWRAP_DEW_CIPHER_MODE] = 0x01a0,
[PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
[PWRAP_DEW_RDDMY_NO] = 0x01a4,
};
static const u32 mt6397_regs[] = {
[PWRAP_DEW_BASE] = 0xbc00,
[PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
[PWRAP_DEW_DIO_EN] = 0xbc02,
[PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
[PWRAP_DEW_EVENT_SRC] = 0xbc06,
[PWRAP_DEW_EVENT_FLAG] = 0xbc08,
[PWRAP_DEW_READ_TEST] = 0xbc0a,
[PWRAP_DEW_WRITE_TEST] = 0xbc0c,
[PWRAP_DEW_CRC_EN] =