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/*
* File: linux/drivers/serial/bfin_sport_uart.c
*
* Based on: drivers/serial/bfin_5xx.c by Aubrey Li.
* Author: Roy Huang <roy.huang@analog.com>
*
* Created: Nov 22, 2006
* Copyright: (c) 2006-2007 Analog Devices Inc.
* Description: this driver enable SPORTs on Blackfin emulate UART.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* This driver and the hardware supported are in term of EE-191 of ADI.
* http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
* This application note describe how to implement a UART on a Sharc DSP,
* but this driver is implemented on Blackfin Processor.
*/
/* After reset, there is a prelude of low level pulse when transmit data first
* time. No addtional pulse in following transmit.
* According to document:
* The SPORTs are ready to start transmitting or receiving data no later than
* three serial clock cycles after they are enabled in the SPORTx_TCR1 or
* SPORTx_RCR1 register. No serial clock cycles are lost from this point on.
* The first internal frame sync will occur one frame sync delay after the
* SPORTs are ready. External frame syncs can occur as soon as the SPORT is
* ready.
*/
/* Thanks to Axel Alatalo <axel@rubico.se> for fixing sport rx bug. Sometimes
* sport receives data incorrectly. The following is Axel's words.
* As EE-191, sport rx samples 3 times of the UART baudrate and takes the
* middle smaple of every 3 samples as the data bit. For a 8-N-1 UART setting,
* 30 samples will be required for a byte. If transmitter sends a 1/3 bit short
* byte due to buadrate drift, then the 30th sample of a byte, this sample is
* also the third sample of the stop bit, will happens on the immediately
* following start bit which will be thrown away and missed. Thus since parts
* of the startbit will be missed and the receiver will begin to drift, the
* effect accumulates over time until synchronization is lost.
* If only require 2 samples of the stopbit (by sampling in total 29 samples),
* then a to short byte as in the case above will be tolerated. Then the 1/3
* early startbit will trigger a framesync since the last read is complete
* after only 2/3 stopbit and framesync is active during the last 1/3 looking
* for a possible early startbit. */
//#define DEBUG
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/platform_device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <asm/delay.h>
#include <asm/portmux.h>
#include "bfin_sport_uart.h"
unsigned short bfin_uart_pin_req_sport0[] =
{P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, \
P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0};
unsigned short bfin_uart_pin_req_sport1[] =
{P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, \
P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0};
#define DRV_NAME "bfin-sport-uart"
struct sport_uart_port {
struct uart_port port;
char *name;
int tx_irq;
int rx_irq;
int err_irq;
};
static void sport_uart_tx_chars(struct sport_uart_port *up);
static void sport_stop_tx(struct uart_port *port);
static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
{
pr_debug("%s value:%x\n", __func__, value);
/* Place a Start and Stop bit */
__asm__ __volatile__ (
"R2 = b#01111111100;"
"R3 = b#10000000001;"
"%0 <<= 2;"
"%0 = %0 & R2;"
"%0 = %0 | R3;"
: "=d"(value)
: "d"(value)
: "ASTAT", "R2", "R3"
);
pr_debug("%s value:%x\n", __func__, value);
SPORT_PUT_TX(up, value);
}
static inline unsigned int rx_one_byte(struct sport_uart_port *up)
{
unsigned int value, extract;
u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
value = SPORT_GET_RX32(up);
pr_debug("%s value:%x\n", __func__, value);
/* Extract 8 bits data */
__asm__ __volatile__ (
"%[extr] = 0;"
"%[mask1] = 0x1801(Z);"
"%[mask2] = 0x0300(Z);"
"%[shift] = 0;"
"LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
".Lloop_s:"
"%[tmp] = extract(%[val], %[mask1].L)(Z);"
"%[tmp] <<= %[shift];"
"%[extr] = %[extr] | %[tmp];"
"%[mask1] = %[mask1] - %[mask2];"
".Lloop_e:"
"%[shift] += 1;"
: [val]"=d"(value), [extr]"=d"(extract), [shift]"=d"(tmp_shift), [tmp]"=d"(tmp),
[mask1]"=d"(tmp_mask1), [mask2]"=d"(tmp_mask2)
: "d"(value), [lc]"a"(8)
: "ASTAT", "LB0", "LC0", "LT0"
);
pr_debug(" extract:%x\n", extract);
return extract;
}
static int sport_uart_setup(struct sport_uart_port *up, int sclk, int baud_rate)
{
int tclkdiv, tfsdiv, rclkdiv;
/* Set TCR1 and TCR2 */
SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
SPORT_PUT_TCR2(up, 10);
pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
/* Set RCR1 and RCR2 */
SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
SPORT_PUT_RCR2(up, 28);
pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
tclkdiv = sclk/(2 * baud_rate) - 1;
tfsdiv = 12;
rclkdiv = sclk/(2 * baud_rate * 3) - 1;
SPORT_PUT_TCLKDIV(up, tclkdiv);
SPORT_PUT_TFSDIV(up, tfsdiv);
SPORT_PUT_RCLKDIV(up, rclkdiv);
SSYNC();
pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, tfsdiv:%d, rclkdiv:%d\n",
__func__, sclk, baud_rate, tclkdiv, tfsdiv, rclkdiv);
return 0;
}
static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
{
struct sport_uart_port *up = dev_id;
struct tty_struct *tty = up->port.state->port.tty;
unsigned int ch;
do {
ch = rx_one_byte(up);
up->port.icount.rx++;
if (uart_handle_sysrq_char(&up->port, ch))
;
else
tty_insert_flip_char(tty, ch, TTY_NORMAL);
} while (SPORT_GET_STAT(up) & RXNE);
tty_flip_buffer_push(tty);
return IRQ_HANDLED;
}
static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
{
sport_uart_tx_chars(dev_id);
return IRQ_HANDLED;
}
static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
{
struct sport_uart_port *up = dev_id;
struct tty_struct *tty = up->port.state->port.tty;
unsigned int stat = SPORT_GET_STAT(up);
/* Overflow in RX FIFO */
if (stat & ROVF) {
up->port.icount.overrun++;
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
}
/* These should not happen */
if (stat & (TOVF | TUVF | RUVF)) {
printk(KERN_ERR "SPORT Error:%s %s %s\n",
(stat & TOVF)?"TX overflow":"",
(stat & TUVF)?"TX underflow":"",
(stat & RUVF)?"RX underflow":"");
SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
}
SSYNC();
return IRQ_HANDLED;
}
/* Reqeust IRQ, Setup clock */
static int sport_startup(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
char buffer[20];
int
|