path: root/drivers/scsi/pm8001/pm8001_hwi.h

/*
 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
 *
 * Copyright (c) 2008-2009 USI Co., Ltd.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    substantially similar to the "NO WARRANTY" disclaimer below
 *    ("Disclaimer") and any redistribution must be conditioned upon
 *    including a substantially similar Disclaimer requirement for further
 *    binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES.
 *
 */
#ifndef _PMC8001_REG_H_
#define _PMC8001_REG_H_

#include <linux/types.h>
#include <scsi/libsas.h>


/* for Request Opcode of IOMB */
#define OPC_INB_ECHO				1	/* 0x000 */
#define OPC_INB_PHYSTART			4	/* 0x004 */
#define OPC_INB_PHYSTOP				5	/* 0x005 */
#define OPC_INB_SSPINIIOSTART			6	/* 0x006 */
#define OPC_INB_SSPINITMSTART			7	/* 0x007 */
#define OPC_INB_SSPINIEXTIOSTART		8	/* 0x008 */
#define OPC_INB_DEV_HANDLE_ACCEPT		9	/* 0x009 */
#define OPC_INB_SSPTGTIOSTART			10	/* 0x00A */
#define OPC_INB_SSPTGTRSPSTART			11	/* 0x00B */
#define OPC_INB_SSPINIEDCIOSTART		12	/* 0x00C */
#define OPC_INB_SSPINIEXTEDCIOSTART		13	/* 0x00D */
#define OPC_INB_SSPTGTEDCIOSTART		14	/* 0x00E */
#define OPC_INB_SSP_ABORT			15	/* 0x00F */
#define OPC_INB_DEREG_DEV_HANDLE		16	/* 0x010 */
#define OPC_INB_GET_DEV_HANDLE			17	/* 0x011 */
#define OPC_INB_SMP_REQUEST			18	/* 0x012 */
/* SMP_RESPONSE is removed */
#define OPC_INB_SMP_RESPONSE			19	/* 0x013 */
#define OPC_INB_SMP_ABORT			20	/* 0x014 */
#define OPC_INB_REG_DEV				22	/* 0x016 */
#define OPC_INB_SATA_HOST_OPSTART		23	/* 0x017 */
#define OPC_INB_SATA_ABORT			24	/* 0x018 */
#define OPC_INB_LOCAL_PHY_CONTROL		25	/* 0x019 */
#define OPC_INB_GET_DEV_INFO			26	/* 0x01A */
#define OPC_INB_FW_FLASH_UPDATE			32	/* 0x020 */
#define OPC_INB_GPIO				34	/* 0x022 */
#define OPC_INB_SAS_DIAG_MODE_START_END		35	/* 0x023 */
#define OPC_INB_SAS_DIAG_EXECUTE		36	/* 0x024 */
#define OPC_INB_SAS_HW_EVENT_ACK		37	/* 0x025 */
#define OPC_INB_GET_TIME_STAMP			38	/* 0x026 */
#define OPC_INB_PORT_CONTROL			39	/* 0x027 */
#define OPC_INB_GET_NVMD_DATA			40	/* 0x028 */
#define OPC_INB_SET_NVMD_DATA			41	/* 0x029 */
#define OPC_INB_SET_DEVICE_STATE		42	/* 0x02A */
#define OPC_INB_GET_DEVICE_STATE		43	/* 0x02B */
#define OPC_INB_SET_DEV_INFO			44	/* 0x02C */
#define OPC_INB_SAS_RE_INITIALIZE		45	/* 0x02D */

/* for Response Opcode of IOMB */
#define OPC_OUB_ECHO				1	/* 0x001 */
#define OPC_OUB_HW_EVENT			4	/* 0x004 */
#define OPC_OUB_SSP_COMP			5	/* 0x005 */
#define OPC_OUB_SMP_COMP			6	/* 0x006 */
#define OPC_OUB_LOCAL_PHY_CNTRL			7	/* 0x007 */
#define OPC_OUB_DEV_REGIST			10	/* 0x00A */
#define OPC_OUB_DEREG_DEV			11	/* 0x00B */
#define OPC_OUB_GET_DEV_HANDLE			12	/* 0x00C */
#define OPC_OUB_SATA_COMP			13	/* 0x00D */
#define OPC_OUB_SATA_EVENT			14	/* 0x00E */
#define OPC_OUB_SSP_EVENT			15	/* 0x00F */
#define OPC_OUB_DEV_HANDLE_ARRIV		16	/* 0x010 */
/* SMP_RECEIVED Notification is removed */
#define OPC_OUB_SMP_RECV_EVENT			17	/* 0x011 */
#define OPC_OUB_SSP_RECV_EVENT			18	/* 0x012 */
#define OPC_OUB_DEV_INFO			19	/* 0x013 */
#define OPC_OUB_FW_FLASH_UPDATE			20	/* 0x014 */
#define OPC_OUB_GPIO_RESPONSE			22	/* 0x016 */
#define OPC_OUB_GPIO_EVENT			23	/* 0x017 */
#define OPC_OUB_GENERAL_EVENT			24	/* 0x018 */
#define OPC_OUB_SSP_ABORT_RSP			26	/* 0x01A */
#define OPC_OUB_SATA_ABORT_RSP			27	/* 0x01B */
#define OPC_OUB_SAS_DIAG_MODE_START_END		28	/* 0x01C */
#define OPC_OUB_SAS_DIAG_EXECUTE		29	/* 0x01D */
#define OPC_OUB_GET_TIME_STAMP			30	/* 0x01E */
#define OPC_OUB_SAS_HW_EVENT_ACK		31	/* 0x01F */
#define OPC_OUB_PORT_CONTROL			32	/* 0x020 */
#define OPC_OUB_SKIP_ENTRY			33	/* 0x021 */
#define OPC_OUB_SMP_ABORT_RSP			34	/* 0x022 */
#define OPC_OUB_GET_NVMD_DATA			35	/* 0x023 */
#define OPC_OUB_SET_NVMD_DATA			36	/* 0x024 */
#define OPC_OUB_DEVICE_HANDLE_REMOVAL		37	/* 0x025 */
#define OPC_OUB_SET_DEVICE_STATE		38	/* 0x026 */
#define OPC_OUB_GET_DEVICE_STATE		39	/* 0x027 */
#define OPC_OUB_SET_DEV_INFO			40	/* 0x028 */
#define OPC_OUB_SAS_RE_INITIALIZE		41	/* 0x029 */

/* for phy start*/
#define SPINHOLD_DISABLE		(0x00 << 14)
#define SPINHOLD_ENABLE			(0x01 << 14)
#define LINKMODE_SAS			(0x01 << 12)
#define LINKMODE_DSATA			(0x02 << 12)
#define LINKMODE_AUTO			(0x03 << 12)
#define LINKRATE_15			(0x01 << 8)
#define LINKRATE_30			(0x02 << 8)
#define LINKRATE_60			(0x04 << 8)

struct mpi_msg_hdr{
	__le32	header;	/* Bits [11:0]  - Message operation code */
	/* Bits [15:12] - Message Category */
	/* Bits [21:16] - Outboundqueue ID for the
	operation completion message */
	/* Bits [23:22] - Reserved */
	/* Bits [28:24] - Buffer Count, indicates how
	many buffer are allocated for the massage */
	/* Bits [30:29] - Reserved */
	/* Bits [31] - Message Valid bit */
} __attribute__((packed, aligned(4)));


/*
 * brief the data structure of PHY Start Command
 * use to describe enable the phy (64 bytes)
 */
struct phy_start_req {
	__le32	tag;
	__le32	ase_sh_lm_slr_phyid;
	struct sas_identify_frame sas_identify;
	u32	reserved[5];
} __attribute__((packed, aligned(4)));


/*
 * brief the data structure of PHY Start Command
 * use to disable the phy (64 bytes)
 */
struct phy_stop_req {
	__le32	tag;
	__le32	phy_id;
	u32	reserved[13];
} __attribute__((packed, aligned(4)));


/* set device bits fis - device to host */
struct  set_dev_bits_fis {
	u8	fis_type;	/* 0xA1*/
	u8	n_i_pmport;
	/* b7 : n Bit. Notification bit. If set device needs attention. */
	/* b6 : i Bit. Interrupt Bit */
	/* b5-b4: reserved2 */
	/* b3-b0: PM Port */
	u8 	status;
	u8	error;
	u32	_r_a;
} __attribute__ ((packed));
/* PIO setup FIS - device to host */
struct  pio_setup_fis {
	u8	fis_type;	/* 0x5f */
	u8	i_d_pmPort;
	/* b7 : reserved */
	/* b6 : i bit. Interrupt bit */
	/* b5 : d bit. data transfer direction. set to 1 for device to host
	xfer */
	/* b4 : reserved */
	/* b3-b0: PM Port */
	u8	status;
	u8	error;
	u8	lbal;
	u8	lbam;
	u8	lbah;
	u8	device;
	u8	lbal_exp;
	u8	lbam_exp;
	u8	lbah_exp;
	u8	_r_a;
	u8	sector_count;
	u8	sector_count_exp;
	u8	_r_b;
	u8	e_status;
	u8	_r_c[2];
	u8	transfer_count;
} __attribute__ ((packed));

/*
 * brief the data structure of SATA Completion Response
 * use to describe the sata task response (64 bytes)
 */
struct sata_completion_resp {
	__le32	tag;
	__le32	status;
	__le32	param;
	u32	sata_resp[12];
} __attribute__((packed, aligned(4)));


/*
 * brief the data structure of SAS HW Event Notification
 * use to alert the host about the hardware event(64 bytes)
 */
struct hw_event_resp {
	__le32	lr_evt_status_phyid_portid;
	__le32	evt_param;
	__le32	npip_portstate;
	struct sas_identify_frame	sas_identify;
	struct dev_to_host_fis	sata_fis;
} __attribute__((packed, aligned(4)));


/*
 * brie