/*****************************************************************************/
/* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
/* */
/* Written By: Keith Mitchell, IBM Corporation */
/* Jack Hammer, Adaptec, Inc. */
/* David Jeffery, Adaptec, Inc. */
/* */
/* Copyright (C) 1999 IBM Corporation */
/* Copyright (C) 2003 Adaptec, Inc. */
/* */
/* This program is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU General Public License as published by */
/* the Free Software Foundation; either version 2 of the License, or */
/* (at your option) any later version. */
/* */
/* This program is distributed in the hope that it will be useful, */
/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* GNU General Public License for more details. */
/* */
/* NO WARRANTY */
/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
/* solely responsible for determining the appropriateness of using and */
/* distributing the Program and assumes all risks associated with its */
/* exercise of rights under this Agreement, including but not limited to */
/* the risks and costs of program errors, damage to or loss of data, */
/* programs or equipment, and unavailability or interruption of operations. */
/* */
/* DISCLAIMER OF LIABILITY */
/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
/* */
/* You should have received a copy of the GNU General Public License */
/* along with this program; if not, write to the Free Software */
/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
/* */
/* Bugs/Comments/Suggestions should be mailed to: */
/* ipslinux@adaptec.com */
/* */
/*****************************************************************************/
#ifndef _IPS_H_
#define _IPS_H_
#include <linux/nmi.h>
#include <asm/uaccess.h>
#include <asm/io.h>
/*
* Some handy macros
*/
#define IPS_HA(x) ((ips_ha_t *) x->hostdata)
#define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
#define IPS_IS_TROMBONE(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
(ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \
(ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0)
#define IPS_IS_CLARINET(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
(ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \
(ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0)
#define IPS_IS_MORPHEUS(ha) (ha->pcidev->device == IPS_DEVICEID_MORPHEUS)
#define IPS_IS_MARCO(ha) (ha->pcidev->device == IPS_DEVICEID_MARCO)
#define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
(IPS_IS_TROMBONE(ha) && \
(ips_force_i2o))) ? 1 : 0)
#define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
(ips_force_memio))) ? 1 : 0)
#define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
#define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
#define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
#define IPS_PRINTK(level, pcidev, format, arg...) \
dev_printk(level , &((pcidev)->dev) , format , ## arg)
#define MDELAY(n) \
do { \
mdelay(n); \
touch_nmi_watchdog(); \
} while (0)
#ifndef min
#define min(x,y) ((x) < (y) ? x : y)
#endif
#ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */
#define __iomem
#endif
#define pci_dma_hi32(a) ((a >> 16) >> 16)
#define pci_dma_lo32(a) (a & 0xffffffff)
#if (BITS_PER_LONG > 32) || defined(CONFIG_HIGHMEM64G)
#define IPS_ENABLE_DMA64 (1)
#else
#define IPS_ENABLE_DMA64 (0)
#endif
/*
* Adapter address map equates
*/
#define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
#define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
#define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
#define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
#define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
#define IPS_REG_SQER 0x28 /* Status Q End Reg */
#define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
#define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
#define IPS_REG_ISPR 0x06 /* interrupt status port reg */
#define IPS_REG_CBSP 0x07 /* CBSP register */
#define IPS_REG_FLAP 0x18 /* Flash address port */
#define IPS_REG_FLDP 0x1C /* Flash data port */
#define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
#define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
#define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
#define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
#define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
#define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
#define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
#define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
/*
* Adapter register bit equates
*/
#define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
#define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
#define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
#define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
#define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
#define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
#define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
#define IPS_BIT_RST 0x80 /* SCPR Reset Bit