path: root/drivers/scsi/be2iscsi/be_main.h

/*
 * Copyright 2017 Broadcom. All Rights Reserved.
 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation. The full GNU General
 * Public License is included in this distribution in the file called COPYING.
 *
 * Contact Information:
 * linux-drivers@broadcom.com
 *
 */

#ifndef _BEISCSI_MAIN_
#define _BEISCSI_MAIN_

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/if_ether.h>
#include <linux/in.h>
#include <linux/ctype.h>
#include <linux/module.h>
#include <linux/aer.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_host.h>
#include <scsi/iscsi_proto.h>
#include <scsi/libiscsi.h>
#include <scsi/scsi_transport_iscsi.h>

#define DRV_NAME		"be2iscsi"
#define BUILD_STR		"11.4.0.1"
#define BE_NAME			"Emulex OneConnect" \
				"Open-iSCSI Driver version" BUILD_STR
#define DRV_DESC		BE_NAME " " "Driver"

#define BE_VENDOR_ID		0x19A2
#define ELX_VENDOR_ID		0x10DF
/* DEVICE ID's for BE2 */
#define BE_DEVICE_ID1		0x212
#define OC_DEVICE_ID1		0x702
#define OC_DEVICE_ID2		0x703

/* DEVICE ID's for BE3 */
#define BE_DEVICE_ID2		0x222
#define OC_DEVICE_ID3		0x712

/* DEVICE ID for SKH */
#define OC_SKH_ID1		0x722

#define BE2_IO_DEPTH		1024
#define BE2_MAX_SESSIONS	256
#define BE2_TMFS		16
#define BE2_NOPOUT_REQ		16
#define BE2_SGE			32
#define BE2_DEFPDU_HDR_SZ	64
#define BE2_DEFPDU_DATA_SZ	8192
#define BE2_MAX_NUM_CQ_PROC	512

#define MAX_CPUS		64U
#define BEISCSI_MAX_NUM_CPUS	7

#define BEISCSI_VER_STRLEN 32

#define BEISCSI_SGLIST_ELEMENTS	30

/**
 * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can
 * be invalidated at a time, consider it before changing the value of
 * BEISCSI_CMD_PER_LUN.
 */
#define BEISCSI_CMD_PER_LUN	128	/* scsi_host->cmd_per_lun */
#define BEISCSI_MAX_SECTORS	1024	/* scsi_host->max_sectors */
#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */

#define BEISCSI_MAX_CMD_LEN	16	/* scsi_host->max_cmd_len */
#define BEISCSI_NUM_MAX_LUN	256	/* scsi_host->max_lun */
#define BEISCSI_MAX_FRAGS_INIT	192

#define BE_SENSE_INFO_SIZE		258
#define BE_ISCSI_PDU_HEADER_SIZE	64
#define BE_MIN_MEM_SIZE			16384
#define MAX_CMD_SZ			65536
#define IIOC_SCSI_DATA                  0x05	/* Write Operation */

/**
 * hardware needs the async PDU buffers to be posted in multiples of 8
 * So have atleast 8 of them by default
 */

#define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num)	\
	(phwi->phwi_ctxt->pasync_ctx[ulp_num])

/********* Memory BAR register ************/
#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET	0xfc
/**
 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 * Disable" may still globally block interrupts in addition to individual
 * interrupt masks; a mechanism for the device driver to block all interrupts
 * atomically without having to arbitrate for the PCI Interrupt Disable bit
 * with the OS.
 */
#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	(1 << 29)	/* bit 29 */

/********* ISR0 Register offset **********/
#define CEV_ISR0_OFFSET				0xC18
#define CEV_ISR_SIZE				4

/**
 * Macros for reading/writing a protection domain or CSR registers
 * in BladeEngine.
 */

#define DB_TXULP0_OFFSET 0x40
#define DB_RXULP0_OFFSET 0xA0
/********* Event Q door bell *************/
#define DB_EQ_OFFSET			DB_CQ_OFFSET
#define DB_EQ_RING_ID_LOW_MASK		0x1FF	/* bits 0 - 8 */
/* Clear the interrupt for this eq */
#define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
/* Must be 1 */
#define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
/* Higher Order EQ_ID bit */
#define DB_EQ_RING_ID_HIGH_MASK	0x1F /* bits 11 - 15 */
#define DB_EQ_HIGH_SET_SHIFT	11
#define DB_EQ_HIGH_FEILD_SHIFT	9
/* Number of event entries processed */
#define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
/* Rearm bit */
#define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */

/********* Compl Q door bell *************/
#define DB_CQ_OFFSET			0x120
#define DB_CQ_RING_ID_LOW_MASK		0x3FF	/* bits 0 - 9 */
/* Higher Order CQ_ID bit */
#define DB_CQ_RING_ID_HIGH_MASK	0x1F /* bits 11 - 15 */
#define DB_CQ_HIGH_SET_SHIFT	11
#define DB_CQ_HIGH_FEILD_SHIFT	10

/* Number of event entries processed */
#define DB_CQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
/* Rearm bit */
#define DB_CQ_REARM_SHIFT		(29)	/* bit 29 */

#define GET_HWI_CONTROLLER_WS(pc)	(pc->phwi_ctrlr)
#define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
		(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
#define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
		(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)

#define PAGES_REQUIRED(x) \
	((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))

#define MEM_DESCR_OFFSET 8
#define BEISCSI_DEFQ_HDR 1
#define BEISCSI_DEFQ_DATA 0
enum be_mem_enum {
	HWI_MEM_ADDN_CONTEXT,
	HWI_MEM_WRB,
	HWI_MEM_WRBH,
	HWI_MEM_SGLH,
	HWI_MEM_SGE,
	HWI_MEM_TEMPLATE_HDR_ULP0,
	HWI_MEM_ASYNC_HEADER_BUF_ULP0,	/* 6 */
	HWI_MEM_ASYNC_DATA_BUF_ULP0,
	HWI_MEM_ASYNC_HEADER_RING_ULP0,
	HWI_MEM_ASYNC_DATA_RING_ULP0,
	HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
	HWI_MEM_ASYNC_DATA_HANDLE_ULP0,	/* 11 */
	HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
	HWI_MEM_TEMPLATE_HDR_ULP1,
	HWI_MEM_ASYNC_HEADER_BUF_ULP1,	/* 14 */
	HWI_MEM_ASYNC_DATA_BUF_ULP1,
	HWI_MEM_ASYNC_HEADER_RING_ULP1,
	HWI_MEM_ASYNC_DATA_RING_ULP1,
	HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
	HWI_MEM_ASYNC_DATA_HANDLE_ULP1,	/* 19 */
	HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
	ISCSI_MEM_GLOBAL_HEADER,
	SE_MEM_MAX
};

struct be_bus_address32 {
	unsigned int address_lo;
	unsigned int address_hi;
};

struct be_bus_address64 {
	unsigned long long address;
};

struct be_bus_address {
	union {
		struct be_bus_address32 a32;
		struct be_bus_address64 a64;
	} u;
};

struct mem_array {
	struct be_bus_address bus_address;	/* Bus address of location */
	void *virtual_address;		/* virtual address to the location */
	unsigned int size;		/* Size required by memory block */
};

struct be_mem_descriptor {
	unsigned int size_in_bytes;	/* Size required by memory block */
	unsigned int num_elements;
	struct mem_array *mem_array;
};

struct sgl_handle {
	unsigned int sgl_index;
	unsigned int type;
	unsigned int cid;
	struct iscsi_task *task;
	struct iscsi_sge *pfrag;
};

struct hba_parameters {
	unsigned int ios_per_ctrl;
	unsigned int cxns_per_ctrl;
	unsigned int icds_per_ctrl;
	unsigned int num_sge_per_io;
	unsigned int defpdu_hdr_sz;
	unsigned int defpdu_data_sz;
	unsigned int num_cq_entries;
	unsigned int num_eq_entries;
	unsigned int wrbs_per_cxn;
	unsigned int hwi_ws_sz;
};

#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
	(phwi_ctrlr->wrb_context[cri].ulp_num)
struct hwi_wrb_context {
	spinlock_t wrb_lock;
	struct wrb_handle **pwrb_handle_base;
	struct wrb_handle **pwrb_handle_basestd;
	struct iscsi_wrb *plast_wrb;
	unsigned short alloc_index;
	unsigned short free_index;
	unsigned short wrb_handles_available;
	unsigned short cid;
	uint8_t ulp_num;	/* ULP to which CID binded */
	uint32_t doorbell_offset;
};

struct ulp_cid_info {
	unsigned short *cid_array;
	unsigned short avlbl_cids;
	un