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/**
* Copyright (C) 2005 - 2011 Emulex
* All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation. The full GNU General
* Public License is included in this distribution in the file called COPYING.
*
* Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
*
* Contact Information:
* linux-drivers@emulex.com
*
* Emulex
* 3333 Susan Street
* Costa Mesa, CA 92626
*/
#ifndef _BEISCSI_MAIN_
#define _BEISCSI_MAIN_
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/if_ether.h>
#include <linux/in.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_host.h>
#include <scsi/iscsi_proto.h>
#include <scsi/libiscsi.h>
#include <scsi/scsi_transport_iscsi.h>
#include "be.h"
#define DRV_NAME "be2iscsi"
#define BUILD_STR "4.1.239.0"
#define BE_NAME "ServerEngines BladeEngine2" \
"Linux iSCSI Driver version" BUILD_STR
#define DRV_DESC BE_NAME " " "Driver"
#define BE_VENDOR_ID 0x19A2
/* DEVICE ID's for BE2 */
#define BE_DEVICE_ID1 0x212
#define OC_DEVICE_ID1 0x702
#define OC_DEVICE_ID2 0x703
/* DEVICE ID's for BE3 */
#define BE_DEVICE_ID2 0x222
#define OC_DEVICE_ID3 0x712
#define BE2_IO_DEPTH 1024
#define BE2_MAX_SESSIONS 256
#define BE2_CMDS_PER_CXN 128
#define BE2_TMFS 16
#define BE2_NOPOUT_REQ 16
#define BE2_SGE 32
#define BE2_DEFPDU_HDR_SZ 64
#define BE2_DEFPDU_DATA_SZ 8192
#define MAX_CPUS 31
#define BEISCSI_SGLIST_ELEMENTS 30
#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
#define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
#define BEISCSI_MAX_FRAGS_INIT 192
#define BE_NUM_MSIX_ENTRIES 1
#define MPU_EP_CONTROL 0
#define MPU_EP_SEMAPHORE 0xac
#define BE2_SOFT_RESET 0x5c
#define BE2_PCI_ONLINE0 0xb0
#define BE2_PCI_ONLINE1 0xb4
#define BE2_SET_RESET 0x80
#define BE2_MPU_IRAM_ONLINE 0x00000080
#define BE_SENSE_INFO_SIZE 258
#define BE_ISCSI_PDU_HEADER_SIZE 64
#define BE_MIN_MEM_SIZE 16384
#define MAX_CMD_SZ 65536
#define IIOC_SCSI_DATA 0x05 /* Write Operation */
#define DBG_LVL 0x00000001
#define DBG_LVL_1 0x00000001
#define DBG_LVL_2 0x00000002
#define DBG_LVL_3 0x00000004
#define DBG_LVL_4 0x00000008
#define DBG_LVL_5 0x00000010
#define DBG_LVL_6 0x00000020
#define DBG_LVL_7 0x00000040
#define DBG_LVL_8 0x00000080
#define SE_DEBUG(debug_mask, fmt, args...) \
do { \
if (debug_mask & DBG_LVL) { \
printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
printk(fmt, ##args); \
} \
} while (0);
#define BE_ADAPTER_UP 0x00000000
#define BE_ADAPTER_LINK_DOWN 0x00000001
/**
* hardware needs the async PDU buffers to be posted in multiples of 8
* So have atleast 8 of them by default
*/
#define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
/********* Memory BAR register ************/
#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
/**
* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
* Disable" may still globally block interrupts in addition to individual
* interrupt masks; a mechanism for the device driver to block all interrupts
* atomically without having to arbitrate for the PCI Interrupt Disable bit
* with the OS.
*/
#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
/********* ISR0 Register offset **********/
#define CEV_ISR0_OFFSET 0xC18
#define CEV_ISR_SIZE 4
/**
* Macros for reading/writing a protection domain or CSR registers
* in BladeEngine.
*/
#define DB_TXULP0_OFFSET 0x40
#define DB_RXULP0_OFFSET 0xA0
/********* Event Q door bell *************/
#define DB_EQ_OFFSET DB_CQ_OFFSET
#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
/* Clear the interrupt for this eq */
#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
/* Must be 1 */
#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
/* Number of event entries processed */
#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
/* Rearm bit */
#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
/********* Compl Q door bell *************/
#define DB_CQ_OFFSET 0x120
#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
/* Number of event entries processed */
#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
/* Rearm bit */
#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
#define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
#define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
#define PAGES_REQUIRED(x) \
((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
enum be_mem_enum {
HWI_MEM_ADDN_CONTEXT,
HWI_MEM_WRB,
HWI_MEM_WRBH,
HWI_MEM_SGLH,
HWI_MEM_SGE,
HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
HWI_MEM_ASYNC_DATA_BUF,
HWI_MEM_ASYNC_HEADER_RING,
HWI_MEM_ASYNC_DATA_RING,
HWI_MEM_ASYNC_HEADER_HANDLE,
HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
HWI_MEM_ASYNC_PDU_CONTEXT,
ISCSI_MEM_GLOBAL_HEADER,
SE_MEM_MAX
};
struct be_bus_address32 {
unsigned int address_lo;
unsigned int address_hi;
};
struct be_bus_address64 {
unsigned long long address;
};
struct be_bus_address {
union {
struct be_bus_address32 a32;
struct be_bus_address64 a64;
} u;
};
struct mem_array {
struct be_bus_address bus_address; /* Bus address of location */
void *virtual_address; /* virtual address to the location */
unsigned int size; /* Size required by memory block */
};
struct be_mem_descriptor {
unsigned int index; /* Index of this memory parameter */
unsigned int category; /* type indicates cached/non-cached */
unsigned int num_elements; /* number of elements in this
* descriptor
*/
unsigned int alignment_mask; /* Alignment mask for this block */
unsigned int size_in_bytes; /* Size required by memory block */
struct mem_array *mem_array;
};
struct sgl_handle {
unsigned int sgl_index;
unsigned int type;
unsigned int cid;
struct iscsi_task *task;
struct iscsi_sge *pfrag;
};
struct hba_parameters {
unsigned int ios_per_ctrl;
unsigned int cxns_per_ctrl;
unsigned int asyncpdus_per_ctrl;
unsigned int icds_per_ctrl;
unsigned int num_sge_per_io;
unsigned int defpdu_hdr_sz;
unsigned int defpdu_data_sz;
unsigned int num_cq_entries;
unsigned int num_eq_entries;
unsigned int wrbs_per_cxn;
unsigned int crashmode;
unsigned int hba_num;
unsigned int mgmt_ws_sz;
unsigned int hwi_ws_sz;
unsigned int eto;
unsigned int ldto;
unsigned int dbg_flags;
unsigned int num_cxn;
unsigned int eq_timer;
/**
* These are calculated from other params. They're here
* for debug purposes
*/
unsigned int num_mcc_pages;
unsigned int num_mcc_cq_pages;
unsigned int num_cq_pages;
unsigned int num_eq_pages;
unsigned int num_async_pdu_buf_pages;
unsigned int num_async_pdu_buf_sgl_pages;
unsigned int num_async_pdu_buf_cq_pages;
unsigned int num_async_pdu_hdr_pages;
unsigned int num_async_pdu_hdr_sgl_pages;
unsigned int num_async_pdu_hdr_cq_pages;
unsigned int num_sge;
};
struct invalidate_command_table {
unsigned short icd;
unsigned short cid;
} __packed;
struct beiscsi_hba {
struct hba_parameters params;
struct hwi_controller *phwi_ctrlr;
unsigned int mem_req[SE_MEM_MAX];
/* PCI BAR mapped addresses */
u8 __iomem *csr_va; /* CSR */
u8 __iomem *db_va; /* Door Bell */
u8 __iomem *pci_va; /* PCI Config */
struct be_bus_address csr_pa; /* CSR */
struct be_bus_address db_pa; /* CSR */
struct be_bus_address pci_pa; /* CSR */
/* PCI representation of our HBA */
struct pci_dev *pcidev;
unsigned int state;
unsigned short asic_revision;
unsigned int num_cpus;
unsigned int nxt_cqid;
struct msix_entry msix_entries[MAX_CPUS + 1];
char *msi_name[MAX_CPUS
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