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|
/*
* AMD am53c974 driver.
* Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <scsi/scsi_host.h>
#include "esp_scsi.h"
#define DRV_MODULE_NAME "am53c974"
#define DRV_MODULE_VERSION "1.00"
static bool am53c974_debug;
static bool am53c974_fenab = true;
#define esp_dma_log(f, a...) \
do { \
if (am53c974_debug) \
shost_printk(KERN_DEBUG, esp->host, f, ##a); \
} while (0)
#define ESP_DMA_CMD 0x10
#define ESP_DMA_STC 0x11
#define ESP_DMA_SPA 0x12
#define ESP_DMA_WBC 0x13
#define ESP_DMA_WAC 0x14
#define ESP_DMA_STATUS 0x15
#define ESP_DMA_SMDLA 0x16
#define ESP_DMA_WMAC 0x17
#define ESP_DMA_CMD_IDLE 0x00
#define ESP_DMA_CMD_BLAST 0x01
#define ESP_DMA_CMD_ABORT 0x02
#define ESP_DMA_CMD_START 0x03
#define ESP_DMA_CMD_MASK 0x03
#define ESP_DMA_CMD_DIAG 0x04
#define ESP_DMA_CMD_MDL 0x10
#define ESP_DMA_CMD_INTE_P 0x20
#define ESP_DMA_CMD_INTE_D 0x40
#define ESP_DMA_CMD_DIR 0x80
#define ESP_DMA_STAT_PWDN 0x01
#define ESP_DMA_STAT_ERROR 0x02
#define ESP_DMA_STAT_ABORT 0x04
#define ESP_DMA_STAT_DONE 0x08
#define ESP_DMA_STAT_SCSIINT 0x10
#define ESP_DMA_STAT_BCMPLT 0x20
/* EEPROM is accessed with 16-bit values */
#define DC390_EEPROM_READ 0x80
#define DC390_EEPROM_LEN 0x40
/*
* DC390 EEPROM
*
* 8 * 4 bytes of per-device options
* followed by HBA specific options
*/
/* Per-device options */
#define DC390_EE_MODE1 0x00
#define DC390_EE_SPEED 0x01
/* HBA-specific options */
#define DC390_EE_ADAPT_SCSI_ID 0x40
#define DC390_EE_MODE2 0x41
#define DC390_EE_DELAY 0x42
#define DC390_EE_TAG_CMD_NUM 0x43
#define DC390_EE_MODE1_PARITY_CHK 0x01
#define DC390_EE_MODE1_SYNC_NEGO 0x02
#define DC390_EE_MODE1_EN_DISC 0x04
#define DC390_EE_MODE1_SEND_START 0x08
#define DC390_EE_MODE1_TCQ 0x10
#define DC390_EE_MODE2_MORE_2DRV 0x01
#define DC390_EE_MODE2_GREATER_1G 0x02
#define DC390_EE_MODE2_RST_SCSI_BUS 0x04
#define DC390_EE_MODE2_ACTIVE_NEGATION 0x08
#define DC390_EE_MODE2_NO_SEEK 0x10
#define DC390_EE_MODE2_LUN_CHECK 0x20
struct pci_esp_priv {
struct esp *esp;
u8 dma_status;
};
static void pci_esp_dma_drain(struct esp *esp);
static inline struct pci_esp_priv *pci_esp_get_priv(struct esp *esp)
{
struct pci_dev *pdev = esp->dev;
return pci_get_drvdata(pdev);
}
static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg)
{
iowrite8(val, esp->regs + (reg * 4UL));
}
static u8 pci_esp_read8(struct esp *esp, unsigned long reg)
{
return ioread8(esp->regs + (reg * 4UL));
}
static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg)
{
return iowrite32(val, esp->regs + (reg * 4UL));
}
static dma_addr_t pci_esp_map_single(struct esp *esp, void *buf,
size_t sz, int dir)
{
return pci_map_single(esp->dev, buf, sz, dir);
}
static int pci_esp_map_sg(struct esp *esp, struct scatterlist *sg,
int num_sg, int dir)
{
return pci_map_sg(esp->dev, sg, num_sg, dir);
}
static void pci_esp_unmap_single(struct esp *esp, dma_addr_t addr,
size_t sz, int dir)
{
pci_unmap_single(esp->dev, addr, sz, dir);
}
static void pci_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
int num_sg, int dir)
{
pci_unmap_sg(esp->dev, sg, num_sg, dir);
}
static int pci_esp_irq_pending(struct esp *esp)
{
struct pci_esp_priv *pep = pci_esp_get_priv(esp);
pep->dma_status = pci_esp_read8(esp, ESP_DMA_STATUS);
esp_dma_log("dma intr dreg[%02x]\n", pep->dma_status);
if (pep->dma_status & (ESP_DMA_STAT_ERROR |
ESP_DMA_STAT_ABORT |
ESP_DMA_STAT_DONE |
ESP_DMA_STAT_SCSIINT))
return 1;
return 0;
}
static void pci_esp_reset_dma(struct esp *esp)
{
/* Nothing to do ? */
}
static void pci_esp_dma_drain(struct esp *esp)
{
u8 resid;
int lim = 1000;
if ((esp->sreg & ESP_STAT_PMASK) == ESP_DOP ||
(esp->sreg & ESP_STAT_PMASK) == ESP_DIP)
/* Data-In or Data-Out, nothing to be done */
return;
while (--lim > 0) {
resid = pci_esp_read8(esp, ESP_FFLAGS) & ESP_FF_FBYTES;
if (resid <= 1)
break;
cpu_relax();
}
/*
* When there is a residual BCMPLT will never be set
* (obviously). But we still have to issue the BLAST
* command, otherwise the data will not being transferred.
* But we'll never know when the BLAST operation is
* finished. So check for some time and give up eventually.
*/
lim = 1000;
pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_BLAST, ESP_DMA_CMD);
while (pci_esp_read8(esp, ESP_DMA_STATUS) & ESP_DMA_STAT_BCMPLT) {
if (--lim == 0)
break;
cpu_relax();
}
pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim, resid);
/* BLAST residual handling is currently untested */
if (WARN_ON_ONCE(resid == 1)) {
struct esp_cmd_entry *ent = esp->active_cmd;
ent->flags |= ESP_CMD_FLAG_RESIDUAL;
}
}
static void pci_esp_dma_invalidate(struct esp *esp)
{
struct pci_esp_priv *pep = pci_esp_get_priv(esp);
esp_dma_log("invalidate DMA\n");
pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
pep->dma_status = 0;
}
static int pci_esp_dma_error(struct esp *esp)
{
struct pci_esp_priv *pep = pci_esp_get_priv(esp);
if (pep->dma_status & ESP_DMA_STAT_ERROR) {
u8 dma_cmd = pci_esp_read8(esp, ESP_DMA_CMD);
if ((dma_cmd & ESP_DMA_CMD_MASK) == ESP_DMA_CMD_START)
pci_esp_write8(esp, ESP_DMA_CMD_ABORT, ESP_DMA_CMD);
return 1;
}
if (pep->dma_status & ESP_DMA_STAT_ABORT) {
pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
pep->dma_status = pci_esp_read8(esp, ESP_DMA_CMD);
return 1;
}
return 0;
}
static void pci_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
u32 dma_count, int write, u8 cmd)
{
struct pci_esp_priv *pep = pci_esp_get_priv(esp);
u32 val = 0;
BUG_ON(!(cmd & ESP_CMD_DMA));
pep->dma_status = 0;
/* Set DMA engine to IDLE */
if (write)
/* DMA write direction logic is inverted */
val |= ESP_DMA_CMD_DIR;
pci_esp_write8(esp, ESP_DMA_CMD_IDLE | val, ESP_DMA_CMD);
pci_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
pci_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
if (esp->config2 & ESP_CONFIG2_FENAB)
pci_esp_write8(esp, (esp_count >> 16) & 0xff, ESP_TCHI);
pci_esp_write32(esp, esp_count, ESP_DMA_STC);
pci_esp_write32(esp, addr, ESP_DMA_SPA);
esp_dma_log("start dma addr[%x] count[%d:%d]\n",
addr, esp_count, dma_count);
scsi_esp_cmd(esp, cmd);
/* Send DMA Start command */
pci_esp_write8(esp, ESP_DMA_CMD_START | val, ESP_DMA_CMD);
}
static u32 pci_esp_dma_length_limit(struct esp *esp, u32
|