/*
* Core definitions and data structures shareable across OS platforms.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $
*
* $FreeBSD$
*/
#ifndef _AIC7XXX_H_
#define _AIC7XXX_H_
/* Register Definitions */
#include "aic7xxx_reg.h"
/************************* Forward Declarations *******************************/
struct ahc_platform_data;
struct scb_platform_data;
struct seeprom_descriptor;
/****************************** Useful Macros *********************************/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#define ALL_CHANNELS '\0'
#define ALL_TARGETS_MASK 0xFFFF
#define INITIATOR_WILDCARD (~0)
#define SCSIID_TARGET(ahc, scsiid) \
(((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
>> TID_SHIFT)
#define SCSIID_OUR_ID(scsiid) \
((scsiid) & OID)
#define SCSIID_CHANNEL(ahc, scsiid) \
((((ahc)->features & AHC_TWIN) != 0) \
? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
: 'A')
#define SCB_IS_SCSIBUS_B(ahc, scb) \
(SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
#define SCB_GET_OUR_ID(scb) \
SCSIID_OUR_ID((scb)->hscb->scsiid)
#define SCB_GET_TARGET(ahc, scb) \
SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
#define SCB_GET_CHANNEL(ahc, scb) \
SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
#define SCB_GET_LUN(scb) \
((scb)->hscb->lun & LID)
#define SCB_GET_TARGET_OFFSET(ahc, scb) \
(SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
#define SCB_GET_TARGET_MASK(ahc, scb) \
(0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
#ifdef AHC_DEBUG
#define SCB_IS_SILENT(scb) \
((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
&& (((scb)->flags & SCB_SILENT) != 0))
#else
#define SCB_IS_SILENT(scb) \
(((scb)->flags & SCB_SILENT) != 0)
#endif
#define TCL_TARGET_OFFSET(tcl) \
((((tcl) >> 4) & TID) >> 4)
#define TCL_LUN(tcl) \
(tcl & (AHC_NUM_LUNS - 1))
#define BUILD_TCL(scsiid, lun) \
((lun) | (((scsiid) & TID) << 4))
#ifndef AHC_TARGET_MODE
#undef AHC_TMODE_ENABLE
#define AHC_TMODE_ENABLE 0
#endif
/**************************** Driver Constants ********************************/
/*
* The maximum number of supported targets.
*/
#define AHC_NUM_TARGETS 16
/*
* The maximum number of supported luns.
* The identify message only supports 64 luns in SPI3.
* You can have 2^64 luns when information unit transfers are enabled,
* but it is doubtful this driver will ever support IUTs.
*/
#define AHC_NUM_LUNS 64
/*
* The maximum transfer per S/G segment.
*/
#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
/*
* The maximum amount of SCB storage in hardware on a controller.
* This value represents an upper bound. Controllers vary in the number
* they actually support.
*/
#define AHC_SCB_MAX 255
/*
* The maximum number of concurrent transactions supported per driver instance.
* Sequencer Control Blocks (SCBs) store per-transaction information. Although
* the space for SCBs on the host adapter varies by model, the driver will
* page the SCBs between host and controller memory as needed. We are limited
* to 253 because:
* 1) The 8bit nature of the RISC engine holds us to an 8bit value.
* 2) We reserve one value, 255, to represent the invalid element.
* 3) Our input queue scheme requires one SCB to always be reserved
* in advance of queuing any SCBs. This takes us down to 254.
* 4) To handle our output queue correctly on machines that only
* support 32bit stores, we must clear the array 4 bytes at a
* time. To avoid colliding with a DMA write from the sequencer,
* we must be sure that 4 slots are empty when we write to clear
* the queue. This reduces us to 253 SCBs: 1 that just completed
* and the known three additional empty slots in the queue that
* precede it.
*/
#define AHC_MAX_QUEUE 253
/*
* The maximum amount of SCB storage we allocate in host memory. This
* number should reflect the 1 additional SCB we require to handle our
* qinfifo mechanism.
*/
#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
/*
* Ring Buffer of incoming target commands.
* We allocate 256 to simplify the logic in the sequencer
* by using the natural wrap point of an 8bit counter.
*/
#define AHC_TMODE_CMDS 256
/* Reset line assertion time in us */
#define AHC_BUSRESET_DELAY 25
/******************* Chip Characteristics/Operating Settings *****************/
/*
* Chip Type
* The chip order is from least sophisticated to most sophisticated.
*/
typedef enum {
AHC_NONE = 0x0000,
AHC_CHIPID_MASK = 0x00FF,
AHC_AIC7770 = 0x0001,
AHC_AIC7850 = 0x0002,
AHC_AIC7855 = 0x0003,
AHC_AIC7859 = 0x0004,
AHC_AIC7860 = 0x0005,
AHC_AIC7870 = 0x0006,
AHC_AIC7880 = 0x0007,
AHC_AIC7895 = 0x0008,
AHC_AIC7895C = 0x0009