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|
/*
* Real Time Clock interface for XScale PXA27x and PXA3xx
*
* Copyright (C) 2008 Robert Jarzmik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <mach/hardware.h>
#define RTC_DEF_DIVIDER (32768 - 1)
#define RTC_DEF_TRIM 0
#define MAXFREQ_PERIODIC 1000
/*
* PXA Registers and bits definitions
*/
#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
#define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */
#define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
#define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
#define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
#define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
#define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
#define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */
#define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */
#define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */
#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
#define RTSR_AL (1 << 0) /* RTC alarm detected */
#define RTSR_TRIG_MASK (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
| RTSR_SWAL1 | RTSR_SWAL2)
#define RYxR_YEAR_S 9
#define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S)
#define RYxR_MONTH_S 5
#define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
#define RYxR_DAY_MASK 0x1f
#define RDxR_WOM_S 20
#define RDxR_WOM_MASK (0x7 << RDxR_WOM_S)
#define RDxR_DOW_S 17
#define RDxR_DOW_MASK (0x7 << RDxR_DOW_S)
#define RDxR_HOUR_S 12
#define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S)
#define RDxR_MIN_S 6
#define RDxR_MIN_MASK (0x3f << RDxR_MIN_S)
#define RDxR_SEC_MASK 0x3f
#define RTSR 0x08
#define RTTR 0x0c
#define RDCR 0x10
#define RYCR 0x14
#define RDAR1 0x18
#define RYAR1 0x1c
#define RTCPICR 0x34
#define PIAR 0x38
#define rtc_readl(pxa_rtc, reg) \
__raw_readl((pxa_rtc)->base + (reg))
#define rtc_writel(pxa_rtc, reg, value) \
__raw_writel((value), (pxa_rtc)->base + (reg))
struct pxa_rtc {
struct resource *ress;
void __iomem *base;
int irq_1Hz;
int irq_Alrm;
struct rtc_device *rtc;
spinlock_t lock; /* Protects this structure */
};
static u32 ryxr_calc(struct rtc_time *tm)
{
return ((tm->tm_year + 1900) << RYxR_YEAR_S)
| ((tm->tm_mon + 1) << RYxR_MONTH_S)
| tm->tm_mday;
}
static u32 rdxr_calc(struct rtc_time *tm)
{
return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
| (tm->tm_hour << RDxR_HOUR_S)
| (tm->tm_min << RDxR_MIN_S)
| tm->tm_sec;
}
static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
{
tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
tm->tm_mday = (rycr & RYxR_DAY_MASK);
tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
tm->tm_sec = rdcr & RDxR_SEC_MASK;
}
static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
u32 rtsr;
rtsr = rtc_readl(pxa_rtc, RTSR);
rtsr &= ~RTSR_TRIG_MASK;
rtsr &= ~mask;
rtc_writel(pxa_rtc, RTSR, rtsr);
}
static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
u32 rtsr;
rtsr = rtc_readl(pxa_rtc, RTSR);
rtsr &= ~RTSR_TRIG_MASK;
rtsr |= mask;
rtc_writel(pxa_rtc, RTSR, rtsr);
}
static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
{
struct platform_device *pdev = to_platform_device(dev_id);
struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
u32 rtsr;
unsigned long events = 0;
spin_lock(&pxa_rtc->lock);
/* clear interrupt sources */
rtsr = rtc_readl(pxa_rtc, RTSR);
rtc_writel(pxa_rtc, RTSR, rtsr);
/* temporary disable rtc interrupts */
rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
/* clear alarm interrupt if it has occurred */
if (rtsr & RTSR_RDAL1)
rtsr &= ~RTSR_RDALE1;
/* update irq data & counter */
if (rtsr & RTSR_RDAL1)
events |= RTC_AF | RTC_IRQF;
if (rtsr & RTSR_HZ)
events |= RTC_UF | RTC_IRQF;
if (rtsr & RTSR_PIAL)
events |= RTC_PF | RTC_IRQF;
rtc_update_irq(pxa_rtc->rtc, 1, events);
/* enable back rtc interrupts */
rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
spin_unlock(&pxa_rtc->lock);
return IRQ_HANDLED;
}
static int pxa_rtc_open(struct device *dev)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
int ret;
ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, 0,
"rtc 1Hz", dev);
if (ret < 0) {
dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz,
ret);
goto err_irq_1Hz;
}
ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, 0,
"rtc Alrm", dev);
if (ret < 0) {
dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm,
ret);
goto err_irq_Alrm;
}
return 0;
err_irq_Alrm:
free_irq(pxa_rtc->irq_1Hz, dev);
err_irq_1Hz:
return ret;
}
static void pxa_rtc_release(struct device *dev)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
spin_lock_irq(&pxa_rtc->lock);
rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
spin_unlock_irq(&pxa_rtc->lock);
free_irq(pxa_rtc->irq_Alrm, dev);
free_irq(pxa_rtc->irq_1Hz, dev);
}
static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
spin_lock_irq(&pxa_rtc->lock);
if (enabled)
rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
else
rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
spin_unlock_irq(&pxa_rtc->lock);
return 0;
}
static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
u32 rycr, rdcr;
rycr = rtc_readl(pxa_rtc, RYCR);
rdcr = rtc_readl(pxa_rtc, RDCR);
tm_calc(rycr, rdcr, tm);
return 0;
}
static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
return 0;
}
static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
u32 rtsr, ryar, rdar;
ryar = rtc_readl(pxa_rtc, RYAR1);
rdar = rtc_readl(pxa_rtc, RDAR1);
tm_calc(ryar, rdar, &alrm->time);
rtsr = rtc_readl(pxa_rtc, RTSR);
alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
return 0;
}
static int pxa_rtc_set_alarm(struct device *
|