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/*
* Copyright (c) 2007 Ben Dooks
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* PWM driver for Samsung SoCs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/export.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>
/* For struct samsung_timer_variant and samsung_pwm_lock. */
#include <clocksource/samsung_pwm.h>
#define REG_TCFG0 0x00
#define REG_TCFG1 0x04
#define REG_TCON 0x08
#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
#define TCFG0_PRESCALER_MASK 0xff
#define TCFG0_PRESCALER1_SHIFT 8
#define TCFG1_MUX_MASK 0xf
#define TCFG1_SHIFT(chan) (4 * (chan))
/*
* Each channel occupies 4 bits in TCON register, but there is a gap of 4
* bits (one channel) after channel 0, so channels have different numbering
* when accessing TCON register. See to_tcon_channel() function.
*
* In addition, the location of autoreload bit for channel 4 (TCON channel 5)
* in its set of bits is 2 as opposed to 3 for other channels.
*/
#define TCON_START(chan) BIT(4 * (chan) + 0)
#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
#define TCON_INVERT(chan) BIT(4 * (chan) + 2)
#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
#define TCON_AUTORELOAD(chan) \
((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
/**
* struct samsung_pwm_channel - private data of PWM channel
* @period_ns: current period in nanoseconds programmed to the hardware
* @duty_ns: current duty time in nanoseconds programmed to the hardware
* @tin_ns: time of one timer tick in nanoseconds with current timer rate
*/
struct samsung_pwm_channel {
u32 period_ns;
u32 duty_ns;
u32 tin_ns;
};
/**
* struct samsung_pwm_chip - private data of PWM chip
* @chip: generic PWM chip
* @variant: local copy of hardware variant data
* @inverter_mask: inverter status for all channels - one bit per channel
* @base: base address of mapped PWM registers
* @base_clk: base clock used to drive the timers
* @tclk0: external clock 0 (can be ERR_PTR if not present)
* @tclk1: external clock 1 (can be ERR_PTR if not present)
*/
struct samsung_pwm_chip {
struct pwm_chip chip;
struct samsung_pwm_variant variant;
u8 inverter_mask;
void __iomem *base;
struct clk *base_clk;
struct clk *tclk0;
struct clk *tclk1;
};
#ifndef CONFIG_CLKSRC_SAMSUNG_PWM
/*
* PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
* and some registers need access synchronization. If both drivers are
* compiled in, the spinlock is defined in the clocksource driver,
* otherwise following definition is used.
*
* Currently we do not need any more complex synchronization method
* because all the supported SoCs contain only one instance of the PWM
* IP. Should this change, both drivers will need to be modified to
* properly synchronize accesses to particular instances.
*/
static DEFINE_SPINLOCK(samsung_pwm_lock);
#endif
static inline
struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
{
return container_of(chip, struct samsung_pwm_chip, chip);
}
static inline unsigned int to_tcon_channel(unsigned int channel)
{
/* TCON register has a gap of 4 bits (1 channel) after channel 0 */
return (channel == 0) ? 0 : (channel + 1);
}
static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm,
unsigned int channel, u8 divisor)
{
u8 shift = TCFG1_SHIFT(channel);
unsigned long flags;
u32 reg;
u8 bits;
bits = (fls(divisor) - 1) - pwm->variant.div_base;
spin_lock_irqsave(&samsung_pwm_lock, flags);
reg = readl(pwm->base + REG_TCFG1);
reg &= ~(TCFG1_MUX_MASK << shift);
reg |= bits << shift;
writel(reg, pwm->base + REG_TCFG1);
spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}
static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan)
{
struct samsung_pwm_variant *variant = &chip->variant;
u32 reg;
reg = readl(chip->base + REG_TCFG1);
reg >>= TCFG1_SHIFT(chan);
reg &= TCFG1_MUX_MASK;
return (BIT(reg) & variant->tclk_mask) == 0;
}
static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip,
unsigned int chan)
{
unsigned long rate;
u32 reg;
rate = clk_get_rate(chip->base_clk);
reg = readl(chip->base + REG_TCFG0);
if (chan >= 2)
reg >>= TCFG0_PRESCALER1_SHIFT;
reg &= TCFG0_PRESCALER_MASK;
return rate / (reg + 1);
}
static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip,
unsigned int chan, unsigned long freq)
{
struct samsung_pwm_variant *variant = &chip->variant;
unsigned long rate;
struct clk *clk;
u8 div;
if (!pwm_samsung_is_tdiv(chip, chan)) {
clk = (chan < 2) ? chip->tclk0 : chip->tclk1;
if (!IS_ERR(clk)) {
rate = clk_get_rate(clk);
if (rate)
return rate;
}
dev_warn(chip->chip.dev,
"tclk of PWM %d is inoperational, using tdiv\n", chan);
}
rate = pwm_samsung_get_tin_rate(chip, chan);
dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate);
/*
* Compare minimum PWM frequency that can be achieved with possible
* divider settings and choose the lowest divisor that can generate
* frequencies lower than requested.
*/
for (div = variant->div_base; div < 4; ++div)
if ((rate >> (variant->bits + div)) < freq)
break;
pwm_samsung_set_divisor(chip, chan, BIT(div));
return rate >> div;
}
static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
struct samsung_pwm_channel *our_chan;
if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
dev_warn(chip->dev,
"tried to request PWM channel %d without output\n",
pwm->hwpwm);
return -EINVAL;
}
our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL);
if (!our_chan)
return -ENOMEM;
pwm_set_chip_data(pwm, our_chan);
return 0;
}
static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
devm_kfree(chip->dev, pwm_get_chip_data(pwm));
pwm_set_chip_data(pwm, NULL);
}
static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
unsigned long flags;
u32 tcon;
spin_lock_irqsave(&samsung_pwm_lock, flags);
tcon = readl(our_chip->base + REG_TCON);
tcon &= ~TCON_START(tcon_chan);
tcon |= TCON_MANUALUPDATE(tcon_chan);
writel(tcon, our_chip->base + REG_TCON);
tcon &= ~TCON_MANUALUPDATE(tcon_chan);
tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
writel(tcon, our_chip->
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