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/*
* intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
*
* (C) Copyright 2008-2010 Intel Corporation
* Author: Sreedhara DS (sreedhara.ds@intel.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*
* SCU runing in ARC processor communicates with other entity running in IA
* core through IPC mechanism which in turn messaging between IA core ad SCU.
* SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
* SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
* IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
* along with other APIs.
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/pm.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <asm/mrst.h>
#include <asm/intel_scu_ipc.h>
/* IPC defines the following message types */
#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
/* Command id associated with message IPCMSG_PCNTRL */
#define IPC_CMD_PCNTRL_W 0 /* Register write */
#define IPC_CMD_PCNTRL_R 1 /* Register read */
#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
/*
* IPC register summary
*
* IPC register blocks are memory mapped at fixed address of 0xFF11C000
* To read or write information to the SCU, driver writes to IPC-1 memory
* mapped registers (base address 0xFF11C000). The following is the IPC
* mechanism
*
* 1. IA core cDMI interface claims this transaction and converts it to a
* Transaction Layer Packet (TLP) message which is sent across the cDMI.
*
* 2. South Complex cDMI block receives this message and writes it to
* the IPC-1 register block, causing an interrupt to the SCU
*
* 3. SCU firmware decodes this interrupt and IPC message and the appropriate
* message handler is called within firmware.
*/
#define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */
#define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */
#define IPC_WWBUF_SIZE 16 /* IPC Write buffer Size */
#define IPC_RWBUF_SIZE 16 /* IPC Read buffer Size */
#define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */
#define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */
static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
static void ipc_remove(struct pci_dev *pdev);
struct intel_scu_ipc_dev {
struct pci_dev *pdev;
void __iomem *ipc_base;
void __iomem *i2c_base;
};
static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
#define PLATFORM_LANGWELL 1
#define PLATFORM_PENWELL 2
static int platform; /* Platform type */
/*
* IPC Read Buffer (Read Only):
* 16 byte buffer for receiving data from SCU, if IPC command
* processing results in response data
*/
#define IPC_READ_BUFFER 0x90
#define IPC_I2C_CNTRL_ADDR 0
#define I2C_DATA_ADDR 0x04
static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
/*
* Command Register (Write Only):
* A write to this register results in an interrupt to the SCU core processor
* Format:
* |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
*/
static inline void ipc_command(u32 cmd) /* Send ipc command */
{
writel(cmd, ipcdev.ipc_base);
}
/*
* IPC Write Buffer (Write Only):
* 16-byte buffer for sending data associated with IPC command to
* SCU. Size of the data is specified in the IPC_COMMAND_REG register
*/
static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
{
writel(data, ipcdev.ipc_base + 0x80 + offset);
}
/*
* Status Register (Read Only):
* Driver will read this register to get the ready/busy status of the IPC
* block and error status of the IPC command that was just processed by SCU
* Format:
* |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
*/
static inline u8 ipc_read_status(void)
{
return __raw_readl(ipcdev.ipc_base + 0x04);
}
static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
{
return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
}
static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
{
return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
}
static inline int busy_loop(void) /* Wait till scu status is busy */
{
u32 status = 0;
u32 loop_count = 0;
status = ipc_read_status();
while (status & 1) {
udelay(1); /* scu processing time is in few u secods */
status = ipc_read_status();
loop_count++;
/* break if scu doesn't reset busy bit after huge retry */
if (loop_count > 100000) {
dev_err(&ipcdev.pdev->dev, "IPC timed out");
return -ETIMEDOUT;
}
}
return (status >> 1) & 1;
}
/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
{
int nc;
u32 offset = 0;
u32 err = 0;
u8 cbuf[IPC_WWBUF_SIZE] = { };
u32 *wbuf = (u32 *)&cbuf;
mutex_lock(&ipclock);
if (ipcdev.pdev == NULL) {
mutex_unlock(&ipclock);
return -ENODEV;
}
if (platform == PLATFORM_LANGWELL) {
/* Entry is 4 bytes for read/write, 5 bytes for read modify */
for (nc = 0; nc < count; nc++, offset += 3) {
cbuf[offset] = addr[nc];
cbuf[offset + 1] = addr[nc] >> 8;
if (id != IPC_CMD_PCNTRL_R)
cbuf[offset + 2] = data[nc];
if (id == IPC_CMD_PCNTRL_M) {
cbuf[offset + 3] = data[nc + 1];
offset += 1;
}
}
for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
ipc_data_writel(wbuf[nc], offset); /* Write wbuff */
if (id != IPC_CMD_PCNTRL_M)
ipc_command((count*4) << 16 | id << 12 | 0 << 8 | op);
else
ipc_command((count*5) << 16 | id << 12 | 0 << 8 | op);
} else {
for (nc = 0; nc < count; nc++, offset += 2) {
cbuf[offset] = addr[nc];
cbuf[offset + 1] = addr[nc] >> 8;
}
if (id == IPC_CMD_PCNTRL_R) {
for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
ipc_data_writel(wbuf[nc], offset);
ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
} else i
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