/*
* Copyright (C) 2017 Sanechips Technology Co., Ltd.
* Copyright 2017 Linaro Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "pinctrl-zx.h"
#define TOP_REG0 0x00
#define TOP_REG1 0x04
#define TOP_REG2 0x08
#define TOP_REG3 0x0c
#define TOP_REG4 0x10
#define TOP_REG5 0x14
#define TOP_REG6 0x18
#define TOP_REG7 0x1c
#define TOP_REG8 0x20
/*
* The pin numbering starts from AON pins with reserved ones included,
* so that register data like offset and bit position for AON pins can
* be calculated from pin number.
*/
enum zx296718_pin {
/* aon_pmm_reg_0 */
I2C3_SCL = 0,
I2C3_SDA = 1,
AON_RESERVED0 = 2,
AON_RESERVED1 = 3,
SEC_EN = 4,
UART0_RXD = 5,
UART0_TXD = 6,
IR_IN = 7,
SPI0_CLK = 8,
SPI0_CS = 9,
SPI0_TXD = 10,
SPI0_RXD = 11,
KEY_COL0 = 12,
KEY_COL1 = 13,
KEY_COL2 = 14,
KEY_ROW0 = 15,
/* aon_pmm_reg_1 */
KEY_ROW1 = 16,
KEY_ROW2 = 17,
HDMI_SCL = 18,
HDMI_SDA = 19,
JTAG_TCK = 20,
JTAG_TRSTN = 21,
JTAG_TMS = 22,
JTAG_TDI = 23,
JTAG_TDO = 24,
I2C0_SCL = 25,
I2C0_SDA = 26,
I2C1_SCL = 27,
I2C1_SDA = 28,
AON_RESERVED2 = 29,
AON_RESERVED3 = 30,
AON_RESERVED4 = 31,
/* aon_pmm_reg_2 */
SPI1_CLK = 32,
SPI1_CS = 33,
SPI1_TXD = 34,
SPI1_RXD = 35,
AON_RESERVED5 = 36,
AON_RESERVED6 = 37,
AUDIO_DET = 38,
SPDIF_OUT = 39,
HDMI_CEC = 40,
HDMI_HPD = 41,
GMAC_25M_OUT = 42,
BOOT_SEL0 = 43,
BOOT_SEL1 = 44,
BOOT_SEL2 = 45,
DEEP_SLEEP_OUT_N = 46,
AON_RESERVED7 = 47,
/* top_pmm_reg_0 */
GMII_GTX_CLK = 48,
GMII_TX_CLK = 49,
GMII_TXD0 = 50,
GMII_TXD1 = 51,
GMII_TXD2 = 52,
GMII_TXD3 = 53,
GMII_TXD4 = 54,
GMII_TXD5 = 55,
GMII_TXD6 = 56,
GMII_TXD7 = 57,
GMII_TX_ER = 58,
GMII_TX_EN = 59,
GMII_RX_CLK = 60,
GMII_RXD0 = 61,
GMII_RXD1 = 62,
GMII_RXD2 = 63,
/* top_pmm_reg_1 */
GMII_RXD3 = 64,
GMII_RXD4 = 65,
GMII_RXD5 = 66,
GMII_RXD6 = 67,
GMII_RXD7 = 68,
GMII_RX_ER = 69,
GMII_RX_DV = 70,
GMII_COL = 71,
GMII_CRS = 72,
GMII_MDC = 73,
GMII_MDIO = 74,
SDIO1_CLK = 75,
SDIO1_CMD = 76,
SDIO1_DATA0 = 77,
SDIO1_DATA1 = 78,
SDIO1_DATA2 = 79,
/* top_pmm_reg_2 */
SDIO1_DATA3 = 80,
SDIO1_CD = 81,
SDIO1_WP = 82,
USIM1_CD = 83,
USIM1_CLK = 84,
USIM1_RST = 85,
/* top_pmm_reg_3 */
USIM1_DATA = 86,
SDIO0_CLK = 87,
SDIO0_CMD = 88,
SDIO0_DATA0 = 89,
SDIO0_DATA1 = 90,
SDIO0_DATA2 = 91,
SDIO0_DATA3 = 92,
SDIO0_CD = 93,
SDIO0_WP = 94,
/* top_pmm_reg_4 */
TSI0_DATA0 = 95,
SPINOR_CLK = 96,
TSI2_DATA = 97,
TSI2_CLK = 98,
TSI2_SYNC = 99,
TSI2_VALID = 100,
SPINOR_CS = 101,
SPINOR_DQ0 = 102,
SPINOR_DQ1 = 103,
SPINOR_DQ2 = 104,
SPINOR_DQ3 = 105,
VGA_HS = 106