path: root/drivers/pinctrl/ti/pinctrl-ti-iodelay.c

/*
 * Support for configuration of IO Delay module found on Texas Instruments SoCs
 * such as DRA7
 *
 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#include "../core.h"
#include "../devicetree.h"

#define DRIVER_NAME	"ti-iodelay"

/**
 * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance
 * @signature_mask: CONFIG_REG mask for the signature bits (see TRM)
 * @signature_value: CONFIG_REG signature value to be written (see TRM)
 * @lock_mask: CONFIG_REG mask for the lock bits (see TRM)
 * @lock_val: CONFIG_REG lock value for the lock bits (see TRM)
 * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM)
 * @binary_data_coarse_mask: CONFIG_REG coarse mask (see TRM)
 * @binary_data_fine_mask: CONFIG_REG fine mask (see TRM)
 * @reg_refclk_offset: Refclk register offset
 * @refclk_period_mask: Refclk mask
 * @reg_coarse_offset: Coarse register configuration offset
 * @coarse_delay_count_mask: Coarse delay count mask
 * @coarse_ref_count_mask: Coarse ref count mask
 * @reg_fine_offset: Fine register configuration offset
 * @fine_delay_count_mask: Fine delay count mask
 * @fine_ref_count_mask: Fine ref count mask
 * @reg_global_lock_offset: Global iodelay module lock register offset
 * @global_lock_mask: Lock mask
 * @global_unlock_val: Unlock value
 * @global_lock_val: Lock value
 * @reg_start_offset: Offset to iodelay registers after the CONFIG_REG_0 to 8
 * @reg_nr_per_pin: Number of iodelay registers for each pin
 * @regmap_config: Regmap configuration for the IODelay region
 */
struct ti_iodelay_reg_data {
	u32 signature_mask;
	u32 signature_value;
	u32 lock_mask;
	u32 lock_val;
	u32 unlock_val;
	u32 binary_data_coarse_mask;
	u32 binary_data_fine_mask;

	u32 reg_refclk_offset;
	u32 refclk_period_mask;

	u32 reg_coarse_offset;
	u32 coarse_delay_count_mask;
	u32 coarse_ref_count_mask;

	u32 reg_fine_offset;
	u32 fine_delay_count_mask;
	u32 fine_ref_count_mask;

	u32 reg_global_lock_offset;
	u32 global_lock_mask;
	u32 global_unlock_val;
	u32 global_lock_val;

	u32 reg_start_offset;
	u32 reg_nr_per_pin;

	struct regmap_config *regmap_config;
};

/**
 * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)
 * @coarse_ref_count: Coarse reference count
 * @coarse_delay_count: Coarse delay count
 * @fine_ref_count: Fine reference count
 * @fine_delay_count: Fine Delay count
 * @ref_clk_period: Reference Clock period
 * @cdpe: Coarse delay parameter
 * @fdpe: Fine delay parameter
 */
struct ti_iodelay_reg_values {
	u16 coarse_ref_count;
	u16 coarse_delay_count;

	u16 fine_ref_count;
	u16 fine_delay_count;

	u16 ref_clk_period;

	u32 cdpe;
	u32 fdpe;
};

/**
 * struct ti_iodelay_cfg - Description of each configuration parameters
 * @offset: Configuration register offset
 * @a_delay: Agnostic Delay (in ps)
 * @g_delay: Gnostic Delay (in ps)
 */
struct ti_iodelay_cfg {
	u16 offset;
	u16 a_delay;
	u16 g_delay;
};

/**
 * struct ti_iodelay_pingroup - Structure that describes one group
 * @cfg: configuration array for the pin (from dt)
 * @ncfg: number of configuration values allocated
 * @config: pinconf "Config" - currently a dummy value
 */
struct ti_iodelay_pingroup {
	struct ti_iodelay_cfg *cfg;
	int ncfg;
	unsigned long config;
};

/**
 * struct ti_iodelay_device - Represents information for a iodelay instance
 * @dev: Device pointer
 * @phys_base: Physical address base of the iodelay device
 * @reg_base: Virtual address base of the iodelay device
 * @regmap: Regmap for this iodelay instance
 * @pctl: Pinctrl device
 * @desc: pinctrl descriptor for pctl
 * @pa: pinctrl pin wise description
 * @reg_data: Register definition data for the IODelay instance
 * @reg_init_conf_values: Initial configuration values.
 */
struct ti_iodelay_device {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *reg_base;
	struct regmap *regmap;

	struct pinctrl_dev *pctl;
	struct pinctrl_desc desc;
	struct pinctrl_pin_desc *pa;

	const struct ti_iodelay_reg_data *reg_data;
	struct ti_iodelay_reg_values reg_init_conf_values;
};

/**
 * ti_iodelay_extract() - extract bits for a field
 * @val: Register value
 * @mask: Mask
 *
 * Return: extracted value which is appropriately shifted
 */
static inline u32 ti_iodelay_extract(u32 val, u32 mask)
{
	return (val & mask) >> __ffs(mask);
}

/**
 * ti_iodelay_compute_dpe() - Compute equation for delay parameter
 * @period: Period to use
 * @ref: Reference Count
 * @delay: Delay count
 * @delay_m: Delay multiplier
 *
 * Return: Computed delay parameter
 */
static inline u32 ti_iodelay_compute_dpe(u16 period, u16 ref, u16 delay,
					 u16 delay_m)
{
	u64 m, d;

	/* Handle overflow conditions */
	m = 10 * (u64)period * (u64)ref;
	d = 2 * (u64)delay * (u64)delay_m;

	/* Truncate result back to 32 bits */
	return div64_u64(m, d);
}

/**
 * ti_iodelay_pinconf_set() - Configure the pin configuration
 * @iod: iodelay device
 * @cfg: Configuration
 *
 * Update the configuration register as per TRM and lockup once done.
 * *IMPORTANT NOTE* SoC TRM does recommend doing iodelay programmation only
 * while in Isolation. But, then, isolation also implies that every pin
 * on the SoC (including DDR) will be isolated out. The only benefit being
 * a glitchless configuration, However, the intent of this driver is purely
 * to support a "glitchy" configuration where applicable.
 *
 * Return: 0 in case of success, else appropriate error value
 */
static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod,
				  struct ti_iodelay_cfg *cfg)
{
	const struct ti_iodelay_reg_data *reg = iod->reg_data;
	struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;
	struct device *dev = iod->dev;
	u32 g_delay_coarse, g_delay_fine;
	u32 a_delay_coarse, a_delay_fine;
	u32 c_elements, f_elements;
	u32 total_delay;
	u32 reg_mask, reg_val, tmp_val;
	int r;

	/* NOTE: Truncation is expected in all division below */
	g_delay_coarse = cfg->g_delay / 920;
	g_delay_fine = ((cfg->g_delay % 920) * 10) / 60;

	a_delay_coarse = cfg->a_delay / ival->cdpe;
	a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe;

	c_elements = g_delay_coarse + a_delay_coarse;
	f_elements = (g_delay_fine + a_delay_fine) / 10;

	if (f_elements