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/*
* S3C24XX specific support for Samsung pinctrl/gpiolib driver.
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This file contains the SamsungS3C24XX specific information required by the
* Samsung pinctrl/gpiolib driver. It also includes the implementation of
* external gpio and wakeup interrupt support.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/of_irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
#include "pinctrl-samsung.h"
#define NUM_EINT 24
#define NUM_EINT_IRQ 6
#define EINT_MAX_PER_GROUP 8
#define EINTPEND_REG 0xa8
#define EINTMASK_REG 0xa4
#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP))
#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88)
#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4)
#define EINT_LEVEL_LOW 0
#define EINT_LEVEL_HIGH 1
#define EINT_EDGE_FALLING 2
#define EINT_EDGE_RISING 4
#define EINT_EDGE_BOTH 6
#define EINT_MASK 0xf
static const struct samsung_pin_bank_type bank_type_1bit = {
.fld_width = { 1, 1, },
.reg_offset = { 0x00, 0x04, },
};
static const struct samsung_pin_bank_type bank_type_2bit = {
.fld_width = { 2, 1, 2, },
.reg_offset = { 0x00, 0x04, 0x08, },
};
#define PIN_BANK_A(pins, reg, id) \
{ \
.type = &bank_type_1bit, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_2BIT(pins, reg, id) \
{ \
.type = &bank_type_2bit, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_NONE, \
.name = id \
}
#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
{ \
.type = &bank_type_2bit, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_WKUP, \
.eint_func = 2, \
.eint_mask = emask, \
.eint_offset = eoffs, \
.name = id \
}
/**
* struct s3c24xx_eint_data: EINT common data
* @drvdata: pin controller driver data
* @domains: IRQ domains of particular EINT interrupts
* @parents: mapped parent irqs in the main interrupt controller
*/
struct s3c24xx_eint_data {
struct samsung_pinctrl_drv_data *drvdata;
struct irq_domain *domains[NUM_EINT];
int parents[NUM_EINT_IRQ];
};
/**
* struct s3c24xx_eint_domain_data: per irq-domain data
* @bank: pin bank related to the domain
* @eint_data: common data
* eint0_3_parent_only: live eints 0-3 only in the main intc
*/
struct s3c24xx_eint_domain_data {
struct samsung_pin_bank *bank;
struct s3c24xx_eint_data *eint_data;
bool eint0_3_parent_only;
};
static int s3c24xx_eint_get_trigger(unsigned int type)
{
switch (type) {
case IRQ_TYPE_EDGE_RISING:
return EINT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
return EINT_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
return EINT_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
return EINT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
return EINT_LEVEL_LOW;
break;
default:
return -EINVAL;
}
}
static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type)
{
/* Edge- and level-triggered interrupts need different handlers */
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
else
irq_set_handler_locked(d, handle_level_irq);
}
static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
struct samsung_pin_bank *bank, int pin)
{
const struct samsung_pin_bank_type *bank_type = bank->type;
unsigned long flags;
void __iomem *reg;
u8 shift;
u32 mask;
u32 val;
/* Make sure that pin is configured as interrupt */
reg = d->virt_base + bank->pctl_offset;
shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
spin_lock_irqsave(&bank->slock, flags);
val = readl(reg);
val &= ~(mask << shift);
val |= bank->eint_func << shift;
writel(val, reg);
spin_unlock_irqrestore(&bank->slock, flags);
}
static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
int index = bank->eint_offset + data->hwirq;
void __iomem *reg;
int trigger;
u8 shift;
u32 val;
trigger = s3c24xx_eint_get_trigger(type);
if (trigger < 0) {
dev_err(d->dev, "unsupported external interrupt type\n");
return -EINVAL;
}
s3c24xx_eint_set_handler(data, type);
/* Set up interrupt trigger */
reg = d->virt_base + EINT_REG(index);
shift = EINT_OFFS(index);
val = readl(reg);
val &= ~(EINT_MASK << shift);
val |= trigger << shift;
writel(val, reg);
s3c24xx_eint_set_function(d, bank, data->hwirq);
return 0;
}
/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
static void s3c2410_eint0_3_ack(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
struct s3c24xx_eint_data *eint_data = ddata->eint_data;
int parent_irq = eint_data->parents[data->hwirq];
struct irq_chip *parent_chip = irq_get_chip(parent_irq);
parent_chip->irq_ack(irq_get_irq_data(parent_irq));
}
static void s3c2410_eint0_3_mask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
struct s3c24xx_eint_data *eint_data = ddata->eint_data;
int parent_irq = eint_data->parents[data->hwirq];
struct irq_chip *parent_chip = irq_get_chip(parent_irq);
parent_chip->irq_mask(irq_get_irq_data(parent_irq));
}
static void s3c2410_eint0_3_unmask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
struct s3c24xx_eint_data *eint_data = ddata->eint_data;
int parent_irq = eint_data->parents[data->hwirq];
struct irq_chip *parent_chip = irq_get_chip(parent_irq);
parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
}
static struct irq_chip s3c2410_eint0_3_chip = {
.name = "s3c2410-eint0_3",
.irq_ack = s3c2410_eint0_3_ack,
.irq_mask = s3c2410_eint0_3_mask,
.irq_unmask = s3c2410_eint0_3_unmask,
.irq_set_type = s3c24xx_eint_type,
};
static void s3c2410_demux_eint0_3(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc
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