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/*
* Generic device tree based pinctrl driver for one register per pin
* type pinmux controllers
*
* Copyright (C) 2012 Texas Instruments, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#define DRIVER_NAME "pinctrl-single"
#define PCS_MUX_NAME "pinctrl-single,pins"
#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
#define PCS_OFF_DISABLED ~0U
/**
* struct pcs_pingroup - pingroups for a function
* @np: pingroup device node pointer
* @name: pingroup name
* @gpins: array of the pins in the group
* @ngpins: number of pins in the group
* @node: list node
*/
struct pcs_pingroup {
struct device_node *np;
const char *name;
int *gpins;
int ngpins;
struct list_head node;
};
/**
* struct pcs_func_vals - mux function register offset and value pair
* @reg: register virtual address
* @val: register value
*/
struct pcs_func_vals {
void __iomem *reg;
unsigned val;
};
/**
* struct pcs_function - pinctrl function
* @name: pinctrl function name
* @vals: register and vals array
* @nvals: number of entries in vals array
* @pgnames: array of pingroup names the function uses
* @npgnames: number of pingroup names the function uses
* @node: list node
*/
struct pcs_function {
const char *name;
struct pcs_func_vals *vals;
unsigned nvals;
const char **pgnames;
int npgnames;
struct list_head node;
};
/**
* struct pcs_data - wrapper for data needed by pinctrl framework
* @pa: pindesc array
* @cur: index to current element
*
* REVISIT: We should be able to drop this eventually by adding
* support for registering pins individually in the pinctrl
* framework for those drivers that don't need a static array.
*/
struct pcs_data {
struct pinctrl_pin_desc *pa;
int cur;
};
/**
* struct pcs_name - register name for a pin
* @name: name of the pinctrl register
*
* REVISIT: We may want to make names optional in the pinctrl
* framework as some drivers may not care about pin names to
* avoid kernel bloat. The pin names can be deciphered by user
* space tools using debugfs based on the register address and
* SoC packaging information.
*/
struct pcs_name {
char name[PCS_REG_NAME_LEN];
};
/**
* struct pcs_device - pinctrl device instance
* @res: resources
* @base: virtual address of the controller
* @size: size of the ioremapped area
* @dev: device entry
* @pctl: pin controller device
* @mutex: mutex protecting the lists
* @width: bits per mux register
* @fmask: function register mask
* @fshift: function register shift
* @foff: value to turn mux off
* @fmax: max number of functions in fmask
* @names: array of register names for pins
* @pins: physical pins on the SoC
* @pgtree: pingroup index radix tree
* @ftree: function index radix tree
* @pingroups: list of pingroups
* @functions: list of functions
* @ngroups: number of pingroups
* @nfuncs: number of functions
* @desc: pin controller descriptor
* @read: register read function to use
* @write: register write function to use
*/
struct pcs_device {
struct resource *res;
void __iomem *base;
unsigned size;
struct device *dev;
struct pinctrl_dev *pctl;
struct mutex mutex;
unsigned width;
unsigned fmask;
unsigned fshift;
unsigned foff;
unsigned fmax;
struct pcs_name *names;
struct pcs_data pins;
struct radix_tree_root pgtree;
struct radix_tree_root ftree;
struct list_head pingroups;
struct list_head functions;
unsigned ngroups;
unsigned nfuncs;
struct pinctrl_desc desc;
unsigned (*read)(void __iomem *reg);
void (*write)(unsigned val, void __iomem *reg);
};
/*
* REVISIT: Reads and writes could eventually use regmap or something
* generic. But at least on omaps, some mux registers are performance
* critical as they may need to be remuxed every time before and after
* idle. Adding tests for register access width for every read and
* write like regmap is doing is not desired, and caching the registers
* does not help in this case.
*/
static unsigned __maybe_unused pcs_readb(void __iomem *reg)
{
return readb(reg);
}
static unsigned __maybe_unused pcs_readw(void __iomem *reg)
{
return readw(reg);
}
static unsigned __maybe_unused pcs_readl(void __iomem *reg)
{
return readl(reg);
}
static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
{
writeb(val, reg);
}
static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
{
writew(val, reg);
}
static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
{
writel(val, reg);
}
static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
{
struct pcs_device *pcs;
pcs = pinctrl_dev_get_drvdata(pctldev);
return pcs->ngroups;
}
static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
unsigned gselector)
{
struct pcs_device *pcs;
struct pcs_pingroup *group;
pcs = pinctrl_dev_get_drvdata(pctldev);
group = radix_tree_lookup(&pcs->pgtree, gselector);
if (!group) {
dev_err(pcs->dev, "%s could not find pingroup%i\n",
__func__, gselector);
return NULL;
}
return group->name;
}
static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
unsigned gselector,
const unsigned **pin
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