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|
/*
* Core driver for the imx pin controller in imx1/21/27
*
* Copyright (C) 2013 Pengutronix
* Author: Markus Pargmann <mpa@pengutronix.de>
*
* Based on pinctrl-imx.c:
* Author: Dong Aisheng <dong.aisheng@linaro.org>
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "core.h"
#include "pinctrl-imx1.h"
struct imx1_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
const struct imx1_pinctrl_soc_info *info;
};
/*
* MX1 register offsets
*/
#define MX1_DDIR 0x00
#define MX1_OCR 0x04
#define MX1_ICONFA 0x0c
#define MX1_ICONFB 0x10
#define MX1_GIUS 0x20
#define MX1_GPR 0x38
#define MX1_PUEN 0x40
#define MX1_PORT_STRIDE 0x100
/*
* MUX_ID format defines
*/
#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
/*
* IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
* control register are seperated into function, output configuration, input
* configuration A, input configuration B, GPIO in use and data direction.
*
* Those controls that are represented by 1 bit have a direct mapping between
* bit position and pin id. If they are represented by 2 bit, the lower 16 pins
* are in the first register and the upper 16 pins in the second (next)
* register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
*/
/*
* Calculates the register offset from a pin_id
*/
static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
{
unsigned int port = pin_id / 32;
return ipctl->base + port * MX1_PORT_STRIDE;
}
/*
* Write to a register with 2 bits per pin. The function will automatically
* use the next register if the pin is managed in the second register.
*/
static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 value, u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
u32 old_val;
u32 new_val;
dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
reg, offset, value);
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
new_val = value & 0x3; /* Make sure value is really 2 bit */
new_val <<= offset;
new_val |= old_val;/* Set new state for pin_id */
writel(new_val, reg);
}
static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 value, u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = pin_id % 32;
int mask = ~BIT_MASK(offset);
u32 old_val;
u32 new_val;
/* Get current state of pins */
old_val = readl(reg);
old_val &= mask;
new_val = value & 0x1; /* Make sure value is really 1 bit */
new_val <<= offset;
new_val |= old_val;/* Set new state for pin_id */
writel(new_val, reg);
}
static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = pin_id % 16;
/* Use the next register if the pin's port pin number is >=16 */
if (pin_id % 32 >= 16)
reg += 0x04;
return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
}
static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
u32 reg_offset)
{
void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
int offset = pin_id % 32;
return !!(readl(reg) & BIT(offset));
}
static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
const struct imx1_pinctrl_soc_info *info,
const char *name)
{
const struct imx1_pin_group *grp = NULL;
int i;
for (i = 0; i < info->ngroups; i++) {
if (!strcmp(info->groups[i].name, name)) {
grp = &info->groups[i];
break;
}
}
return grp;
}
static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->ngroups;
}
static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
return info->groups[selector].name;
}
static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned int **pins,
unsigned *npins)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
if (selector >= info->ngroups)
return -EINVAL;
*pins = info->groups[selector].pin_ids;
*npins = info->groups[selector].npins;
return 0;
}
static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
imx1_read_bit(ipctl, offset, MX1_GIUS),
imx1_read_bit(ipctl, offset, MX1_GPR),
imx1_read_bit(ipctl, offset, MX1_DDIR),
imx1_read_2bit(ipctl, offset, MX1_OCR),
imx1_read_2bit(ipctl, offset, MX1_ICONFA),
imx1_read_2bit(ipctl, offset, MX1_ICONFB));
}
static int imx1_dt_node_to_map(struct pinctrl_dev *
|