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/*
* Copyright (c) 2016 John Crispin <blogic@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt7623.h"
static const struct mtk_drv_group_desc mt7623_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
#define DRV_SEL0 0xf50
#define DRV_SEL1 0xf60
#define DRV_SEL2 0xf70
#define DRV_SEL3 0xf80
#define DRV_SEL4 0xf90
#define DRV_SEL5 0xfa0
#define DRV_SEL6 0xfb0
#define DRV_SEL7 0xfe0
#define DRV_SEL8 0xfd0
#define DRV_SEL9 0xff0
#define DRV_SEL10 0xf00
#define MSDC0_CTRL0 0xcc0
#define MSDC0_CTRL1 0xcd0
#define MSDC0_CTRL2 0xce0
#define MSDC0_CTRL3 0xcf0
#define MSDC0_CTRL4 0xd00
#define MSDC0_CTRL5 0xd10
#define MSDC0_CTRL6 0xd20
#define MSDC1_CTRL0 0xd30
#define MSDC1_CTRL1 0xd40
#define MSDC1_CTRL2 0xd50
#define MSDC1_CTRL3 0xd60
#define MSDC1_CTRL4 0xd70
#define MSDC1_CTRL5 0xd80
#define MSDC1_CTRL6 0xd90
#define IES_EN0 0xb20
#define IES_EN1 0xb30
#define IES_EN2 0xb40
#define SMT_EN0 0xb50
#define SMT_EN1 0xb60
#define SMT_EN2 0xb70
static const struct mtk_pin_drv_grp mt7623_pin_drv[] = {
MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1),
MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1),
MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1),
MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1),
MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1),
MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1),
MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1),
MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0),
MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0),
MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0),
MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0),
MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0),
MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0),
MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0),
MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0),
MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0),
MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1),
MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1),
MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1),
MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1),
MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0),
MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0),
MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0),
MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0),
MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0),
MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0),
MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0),
MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0),
MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0),
MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1),
MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1),
MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1),
MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1),
MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1),
MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1),
MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1),
MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1),
MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1),
MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1),
MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1),
MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0),
MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0),
MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0),
MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0),
MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0),
MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0),
MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP
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