// SPDX-License-Identifier: GPL-2.0
/*
* Intel Broxton SoC pinctrl/GPIO driver
*
* Copyright (C) 2015, 2016 Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define BXT_PAD_OWN 0x020
#define BXT_PADCFGLOCK 0x060
#define BXT_HOSTSW_OWN 0x080
#define BXT_GPI_IS 0x100
#define BXT_GPI_IE 0x110
#define BXT_COMMUNITY(s, e) \
{ \
.padown_offset = BXT_PAD_OWN, \
.padcfglock_offset = BXT_PADCFGLOCK, \
.hostown_offset = BXT_HOSTSW_OWN, \
.is_offset = BXT_GPI_IS, \
.ie_offset = BXT_GPI_IE, \
.gpp_size = 32, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
}
/* BXT */
static const struct pinctrl_pin_desc bxt_north_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "PWM0"),
PINCTRL_PIN(35, "PWM1"),
PINCTRL_PIN(36, "PWM2"),
PINCTRL_PIN(37, "PWM3"),
PINCTRL_PIN(38, "LPSS_UART0_RXD"),
PINCTRL_PIN(39, "LPSS_UART0_TXD"),
PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
PINCTRL_PIN(42, "LPSS_UART1_RXD"),
PINCTRL_PIN(43, "LPSS_UART1_TXD"),
PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
PINCTRL_PIN(46, "LPSS_UART2_RXD"),
PINCTRL_PIN(47, "LPSS_UART2_TXD"),
PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
PINCTRL_PIN(50, "ISH_UART0_RXD"),
PINCTRL_PIN(51, "ISH_UART0_TXT"),
PINCTRL_PIN(52, "ISH_UART0_RTS_B"),
PINCTRL_PIN(53, "ISH_UART0_CTS_B"),
PINCTRL_PIN(54, "ISH_UART1_RXD"),
PINCTRL_PIN(55, "ISH_UART1_TXT"),
PINCTRL_PIN(56, "ISH_UART1_RTS_B"),
PINCTRL_PIN(57, "ISH_UART1_CTS_B"),
PINCTRL_PIN(58, "ISH_UART2_RXD"),
PINCTRL_PIN(59, "ISH_UART2_TXD"),
PINCTRL_PIN(60, "ISH_UART2_RTS_B"),
PINCTRL_PIN(61, "ISH_UART2_CTS_B"),
PINCTRL_PIN(62, "GP_CAMERASB00"),
PINCTRL_PIN(63, "GP_CAMERASB01"),
PINCTRL_PIN(64, "GP_CAMERASB02"),
PINCTRL_PIN(65, "GP_CAMERASB03"),
PINCTRL_PIN(66, "GP_CAMERASB04"),
PINCTRL_PIN(67, "GP_CAMERASB05"),
PINCTRL_PIN(68, "GP_CAMERASB06"),
PINCTRL_PIN(69, "GP_CAMERASB07"),
PINCTRL_PIN(70, "GP_CAMERASB08"),
PINCTRL_PIN(71, "GP_CAMERASB09"),
PINCTRL_PIN(72, "GP_CAMERASB10"),
PINCTRL_PIN(73, "GP_CAMERASB11"),
PINCTRL_PIN(74, "TCK"),
PINCTRL_PIN(75, "TRST_B"),
PINCTRL_PIN(76, "TMS"),
PINCTRL_PIN(77, "TDI"),
PINCTRL_PIN(78, "CX_PMODE"),
PINCTRL_PIN(79, "CX_PREQ_B"),
PINCTRL_PIN(80, "JTAGX"),
PINCTRL_PIN(81, "CX_PRDY_B"),
PINCTRL_PIN(82, "TDO"),
};
static const unsigned int bxt_north_pwm0_pins[] = {