/*
* ti113x.h 1.16 1999/10/25 20:03:34
*
* The contents of this file are subject to the Mozilla Public License
* Version 1.1 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License
* at http://www.mozilla.org/MPL/
*
* Software distributed under the License is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
* the License for the specific language governing rights and
* limitations under the License.
*
* The initial developer of the original code is David A. Hinds
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in which
* case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use
* your version of this file under the MPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the MPL or the GPL.
*/
#ifndef _LINUX_TI113X_H
#define _LINUX_TI113X_H
/* Register definitions for TI 113X PCI-to-CardBus bridges */
/* System Control Register */
#define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */
#define TI113X_SCR_SMIROUTE 0x04000000
#define TI113X_SCR_SMISTATUS 0x02000000
#define TI113X_SCR_SMIENB 0x01000000
#define TI113X_SCR_VCCPROT 0x00200000
#define TI113X_SCR_REDUCEZV 0x00100000
#define TI113X_SCR_CDREQEN 0x00080000
#define TI113X_SCR_CDMACHAN 0x00070000
#define TI113X_SCR_SOCACTIVE 0x00002000
#define TI113X_SCR_PWRSTREAM 0x00000800
#define TI113X_SCR_DELAYUP 0x00000400
#define TI113X_SCR_DELAYDOWN 0x00000200
#define TI113X_SCR_INTERROGATE 0x00000100
#define TI113X_SCR_CLKRUN_SEL 0x00000080
#define TI113X_SCR_PWRSAVINGS 0x00000040
#define TI113X_SCR_SUBSYSRW 0x00000020
#define TI113X_SCR_CB_DPAR 0x00000010
#define TI113X_SCR_CDMA_EN 0x00000008
#define TI113X_SCR_ASYNC_IRQ 0x00000004
#define TI113X_SCR_KEEPCLK 0x00000002
#define TI113X_SCR_CLKRUN_ENA 0x00000001
#define TI122X_SCR_SER_STEP 0xc0000000
#define TI122X_SCR_INTRTIE 0x20000000
#define TIXX21_SCR_TIEALL 0x10000000
#define TI122X_SCR_CBRSVD 0x00400000
#define TI122X_SCR_MRBURSTDN 0x00008000
#define TI122X_SCR_MRBURSTUP 0x00004000
#define TI122X_SCR_RIMUX 0x00000001
/* Multimedia Control Register */
#define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */
#define TI1250_MMC_ZVOUTEN 0x80
#define TI1250_MMC_PORTSEL 0x40
#define TI1250_MMC_ZVEN1 0x02
#define TI1250_MMC_ZVEN0 0x01
#define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */
#define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */
#define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */
#define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */
#define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */
#define TI1250_GPIO_MODE_MASK 0xc0
/* IRQMUX/MFUNC Register */
#define TI122X_MFUNC 0x008c /* 32 bit */
#define TI122X_MFUNC0_MASK 0x0000000f
#define TI122X_MFUNC1_MASK 0x000000f0
#define TI122X_MFUNC2_MASK 0x00000f00
#define TI122X_MFUNC3_MASK 0x0000f000
#define TI122X_MFUNC4_MASK 0x000f0000
#define TI122X_MFUNC5_MASK 0x00f00000
#define TI122X_MFUNC6_MASK 0x0f000000
#define TI122X_MFUNC0_INTA 0x00000002
#define TI125X_MFUNC0_INTB 0x00000001
#define TI122X_MFUNC1_INTB 0x00000020
#define TI122X_MFUNC3_IRQSER 0x00001000
/* Retry Status Register */
#define TI113X_RETRY_STATUS 0x0090 /* 8 bit */
#define TI113X_RSR_PCIRETRY 0x80
#define TI113X_RSR_CBRETRY 0x40
#define TI113X_RSR_TEXP_CBB 0x20
#define TI113X_RSR_MEXP_CBB 0x10
#define TI113X_RSR_TEXP_CBA 0x08
#define TI113X_RSR_MEXP_CBA 0x04
#define TI113X_RSR_TEXP_PCI 0x02
#define TI113X_RSR_MEXP_PCI 0x01
/* Card Control Register */
#define TI113X_CARD_CONTROL 0x0091 /* 8 bit */
#define TI113X_CCR_RIENB 0x80
#define TI113X_CCR_ZVENABLE 0x40
#define TI113X_CCR_PCI_IRQ_ENA 0x20
#define TI113X_CCR_PCI_IREQ 0x10
#define TI113X_CCR_PCI_CSC 0x08
#define TI113X_CCR_SPKROUTEN 0x02
#define TI113X_CCR_IFG 0x01
#define TI1220_CCR_PORT_SEL 0x20
#define TI122X_CCR_AUD2MUX 0x04
/* Device Control Register */
#define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */
#define TI113X_DCR_5V_FORCE 0x40
#define TI113X_DCR_3V_FORCE 0x20
#define TI113X_DCR_IMODE_MASK 0x06
#define TI113X_DCR_IMODE_ISA 0x02
#define TI113X_DCR_IMODE_SERIAL 0x04
#define TI12XX_DCR_IMODE_PCI_ONLY 0x00
#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
/* Buffer Control Register */
#define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */
#define TI113X_BCR_CB_READ_DEPTH 0x08
#define TI113X_BCR_CB_WRITE_DEPTH 0x04
#define TI113X_BCR_PCI_READ_DEPTH 0x02
#define TI113X_BCR_PCI_WRITE_DEPTH 0x01
/* Diagnostic Register */
#define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */
#define TI1250_DIAG_TRUE_VALUE 0x80
#define TI1250_DIAG_PCI_IREQ 0x40
#define TI1250_DIAG_PCI_CSC 0x20
#define TI1250_DIAG_ASYNC_CSC 0x01
/* DMA Registers */
#define TI113X_DMA_0 0x0094 /* 32 bit */
#define TI113X_DMA_1 0x0098 /* 32 bit */
/* ExCA IO offset registers */
#define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
/* EnE test register */
#define ENE_TEST_C9 0xc9 /* 8bit */
#define ENE_TEST_C9_TLTENABLE 0x02
#define ENE_TEST_C9_PFENABLE_F0 0x04
#define ENE_TEST_C9_PFENABLE_F1 0x08
#define ENE_TEST_C9_PFENABLE (ENE_TEST_C9_PFENABLE_F0 | ENE_TEST_C9_PFENABLE_F1)
#define ENE_TEST_C9_WPDISALBLE_F0 0x40
#define ENE_TEST_C9_WPDISALBLE_F1 0x80
#define ENE_TEST_C9_WPDISALBLE (ENE_TEST_C9_WPDISALBLE_F0 | ENE_TEST_C9_WPDISALBLE_F1)
/*
* Texas Instruments CardBus controller overrides.
*/
#define ti_sysctl(socket) ((socket)->private[0])
#define ti_cardctl(socket) ((socket)->private[1])
#define ti_devctl(socket) ((socket)->private[2])
#define ti_diag(socket) ((socket)->private[3])
#define ti_mfunc(socket) ((socket)->private[4])
#define ene_test_c9(socket) ((socket)->private[5])
/*
* These are the TI specific power management handlers.
*/
static void ti_save_state(struct yenta_socket *socket)
{
ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL);
ti_mfunc(socket) = config_readl(socket, TI122X_MFUNC);
ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL);
ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL);
ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC);
if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
ene_test_c9(socket) = config_readb(socket, ENE_TEST_C9);
}
static void ti_restore_state(struct yenta_socket *socket)
{
config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket));
config_writel(socket, TI122X_MFUNC, ti_mfunc(socket));
config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket));
config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket));
config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket));
if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
config_writeb(socket, ENE_TEST_C9, ene_test_c9(socket));
}
/*
* Zoom video control for TI122x/113x chips
*/
static void ti_zoom_video(struct pcmcia_socket *sock, int onoff)
{
u8 reg;
struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
/* If we don't have a Zoom Video switch this is harmless,
we just tristate the unused (ZV) lines */
reg = config_readb(socket, TI113X_CARD_CONTROL);
if (onoff)
/* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
reg |= TI113X_CCR_ZVENABLE;
else
reg &= ~TI113X_CCR_ZVENABLE;
config_writeb(socket, TI113X_CARD_CONTROL, reg);
}
/*
* The 145x series can also use this. They have an additional
* ZV autodetect mode we don't use but don't actually need.
* FIXME: manual says its in func0 and func1 but disagrees with
* itself about this - do we need to force func0, if so we need
* to know a lot more about socket pairings in pcmcia_socket than
* we do now.. uggh.
*/
static void ti1250_zoom_video(struct pcmcia_socket *sock, int onoff)
{
struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
int shift = 0;
u8 reg;
ti_zoom_video(sock, onoff);
reg = config_readb(socket, TI1250_MULTIMEDIA_CTL);
reg |= TI1250_MMC_ZVOUTEN; /* ZV bus enable */
if(PCI_FUNC(socket->dev->devfn)==1)
shift = 1;
if(onoff)
{
reg &= ~(1<<6); /* Clear select bit */
reg |= shift<<6; /* Favour our socket */
reg |=