path: root/drivers/pci/controller/pcie-mobiveil.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCIe host controller driver for Mobiveil PCIe Host controller
 *
 * Copyright (c) 2018 Mobiveil Inc.
 * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

/* register offsets and bit positions */

/*
 * translation tables are grouped into windows, each window registers are
 * grouped into blocks of 4 or 16 registers each
 */
#define PAB_REG_BLOCK_SIZE	16
#define PAB_EXT_REG_BLOCK_SIZE	4

#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE))
#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * PAB_EXT_REG_BLOCK_SIZE))

#define LTSSM_STATUS		0x0404
#define  LTSSM_STATUS_L0_MASK	0x3f
#define  LTSSM_STATUS_L0	0x2d

#define PAB_CTRL		0x0808
#define  AMBA_PIO_ENABLE_SHIFT	0
#define  PEX_PIO_ENABLE_SHIFT	1
#define  PAGE_SEL_SHIFT	13
#define  PAGE_SEL_MASK		0x3f
#define  PAGE_LO_MASK		0x3ff
#define  PAGE_SEL_EN		0xc00
#define  PAGE_SEL_OFFSET_SHIFT	10

#define PAB_AXI_PIO_CTRL	0x0840
#define  APIO_EN_MASK		0xf

#define PAB_PEX_PIO_CTRL	0x08c0
#define  PIO_ENABLE_SHIFT	0

#define PAB_INTP_AMBA_MISC_ENB		0x0b0c
#define PAB_INTP_AMBA_MISC_STAT	0x0b1c
#define  PAB_INTP_INTX_MASK		0x01e0
#define  PAB_INTP_MSI_MASK		0x8

#define PAB_AXI_AMAP_CTRL(win)	PAB_REG_ADDR(0x0ba0, win)
#define  WIN_ENABLE_SHIFT	0
#define  WIN_TYPE_SHIFT	1

#define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0, win)

#define PAB_AXI_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x0ba4, win)
#define  AXI_WINDOW_ALIGN_MASK		3

#define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8, win)
#define  PAB_BUS_SHIFT		24
#define  PAB_DEVICE_SHIFT	19
#define  PAB_FUNCTION_SHIFT	16

#define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac, win)
#define PAB_INTP_AXI_PIO_CLASS		0x474

#define PAB_PEX_AMAP_CTRL(win)	PAB_REG_ADDR(0x4ba0, win)
#define  AMAP_CTRL_EN_SHIFT	0
#define  AMAP_CTRL_TYPE_SHIFT	1

#define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)
#define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)
#define PAB_PEX_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x4ba8, win)
#define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)

/* starting offset of INTX bits in status register */
#define PAB_INTX_START	5

/* supported number of MSI interrupts */
#define PCI_NUM_MSI	16

/* MSI registers */
#define MSI_BASE_LO_OFFSET	0x04
#define MSI_BASE_HI_OFFSET	0x08
#define MSI_SIZE_OFFSET	0x0c
#define MSI_ENABLE_OFFSET	0x14
#define MSI_STATUS_OFFSET	0x18
#define MSI_DATA_OFFSET	0x20
#define MSI_ADDR_L_OFFSET	0x24
#define MSI_ADDR_H_OFFSET	0x28

/* outbound and inbound window definitions */
#define WIN_NUM_0		0
#define WIN_NUM_1		1
#define CFG_WINDOW_TYPE	0
#define IO_WINDOW_TYPE		1
#define MEM_WINDOW_TYPE	2
#define IB_WIN_SIZE		((u64)256 * 1024 * 1024 * 1024)
#define MAX_PIO_WINDOWS	8

/* Parameters for the waiting for link up routine */
#define LINK_WAIT_MAX_RETRIES	10
#define LINK_WAIT_MIN	90000
#define LINK_WAIT_MAX	100000

struct mobiveil_msi {			/* MSI information */
	struct mutex lock;		/* protect bitmap variable */
	struct irq_domain *msi_domain;
	struct irq_domain *dev_domain;
	phys_addr_t msi_pages_phys;
	int num_of_vectors;
	DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
};

struct mobiveil_pcie {
	struct platform_device *pdev;
	struct list_head resources;
	void __iomem *config_axi_slave_base;	/* endpoint config base */
	void __iomem *csr_axi_slave_base;	/* root port config base */
	void __iomem *apb_csr_base;	/* MSI register base */
	void __iomem *pcie_reg_base;	/* Physical PCIe Controller Base */
	struct irq_domain *intx_domain;
	raw_spinlock_t intx_mask_lock;
	int irq;
	int apio_wins;
	int ppio_wins;
	int ob_wins_configured;		/* configured outbound windows */
	int ib_wins_configured;		/* configured inbound windows */
	struct resource *ob_io_res;
	char root_bus_nr;
	struct mobiveil_msi msi;
};

static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,
		const u32 reg)
{
	writel_relaxed(value, pcie->csr_axi_slave_base + reg);
}

static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)
{
	return readl_relaxed(pcie->csr_axi_slave_base + reg);
}

static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
{
	return (csr_readl(pcie, LTSSM_STATUS) &
		LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
}

static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
{
	struct mobiveil_pcie *pcie = bus->sysdata;

	/* Only one device down on each root port */
	if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
		return false;

	/*
	 * Do not read more than one device on the bus directly
	 * attached to RC
	 */
	if ((bus->primary == pcie->root_bus_nr) && (devfn > 0))
		return false;

	return true;
}

/*
 * mobiveil_pcie_map_bus - routine to get the configuration base of either
 * root port or endpoint
 */
static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
					unsigned int devfn, int where)
{
	struct mobiveil_pcie *pcie = bus->sysdata;

	if (!mobiveil_pcie_valid_device(bus, devfn))
		return NULL;

	if (bus->number == pcie->root_bus_nr) {
		/* RC config access */
		return pcie->csr_axi_slave_base + where;
	}

	/*
	 * EP config access (in Config/APIO space)
	 * Program PEX Address base (31..16 bits) with appropriate value
	 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
	 * Relies on pci_lock serialization
	 */
	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |
			PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
			PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT,
			PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
	return pcie->config_axi_slave_base + where;
}

static struct pci_ops mobiveil_pcie_ops = {
	.map_bus = mobiveil_pcie_map_bus,
	.read = pci_generic_config_read,
	.write = pci_generic_config_write,
};

static void mobiveil_pcie_isr(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
	struct device *dev = &pcie->pdev->dev;
	struct mobiveil_msi *msi = &pcie->msi;
	u32 msi_data, msi_addr_lo, msi_addr_hi;
	u32 intr_status, msi_status;
	unsigned long shifted_status;
	u32 bit, virq, val, mask;

	/*
	 * The core provides a single interrupt for both INTx/MSI messages.
	 * So we'll read both INTx and MSI status
	 */

	chained_irq_enter(chip, desc);

	/* read INTx status */
	val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
	mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
	intr_status = val