/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is part of wl1271
*
* Copyright (C) 2009 Nokia Corporation
*
* Contact: Luciano Coelho <luciano.coelho@nokia.com>
*/
#ifndef __CONF_H__
#define __CONF_H__
enum {
CONF_HW_BIT_RATE_1MBPS = BIT(0),
CONF_HW_BIT_RATE_2MBPS = BIT(1),
CONF_HW_BIT_RATE_5_5MBPS = BIT(2),
CONF_HW_BIT_RATE_6MBPS = BIT(3),
CONF_HW_BIT_RATE_9MBPS = BIT(4),
CONF_HW_BIT_RATE_11MBPS = BIT(5),
CONF_HW_BIT_RATE_12MBPS = BIT(6),
CONF_HW_BIT_RATE_18MBPS = BIT(7),
CONF_HW_BIT_RATE_22MBPS = BIT(8),
CONF_HW_BIT_RATE_24MBPS = BIT(9),
CONF_HW_BIT_RATE_36MBPS = BIT(10),
CONF_HW_BIT_RATE_48MBPS = BIT(11),
CONF_HW_BIT_RATE_54MBPS = BIT(12),
CONF_HW_BIT_RATE_MCS_0 = BIT(13),
CONF_HW_BIT_RATE_MCS_1 = BIT(14),
CONF_HW_BIT_RATE_MCS_2 = BIT(15),
CONF_HW_BIT_RATE_MCS_3 = BIT(16),
CONF_HW_BIT_RATE_MCS_4 = BIT(17),
CONF_HW_BIT_RATE_MCS_5 = BIT(18),
CONF_HW_BIT_RATE_MCS_6 = BIT(19),
CONF_HW_BIT_RATE_MCS_7 = BIT(20),
CONF_HW_BIT_RATE_MCS_8 = BIT(21),
CONF_HW_BIT_RATE_MCS_9 = BIT(22),
CONF_HW_BIT_RATE_MCS_10 = BIT(23),
CONF_HW_BIT_RATE_MCS_11 = BIT(24),
CONF_HW_BIT_RATE_MCS_12 = BIT(25),
CONF_HW_BIT_RATE_MCS_13 = BIT(26),
CONF_HW_BIT_RATE_MCS_14 = BIT(27),
CONF_HW_BIT_RATE_MCS_15 = BIT(28),
};
enum {
CONF_HW_RATE_INDEX_1MBPS = 0,
CONF_HW_RATE_INDEX_2MBPS = 1,
CONF_HW_RATE_INDEX_5_5MBPS = 2,
CONF_HW_RATE_INDEX_11MBPS = 3,
CONF_HW_RATE_INDEX_6MBPS = 4,
CONF_HW_RATE_INDEX_9MBPS = 5,
CONF_HW_RATE_INDEX_12MBPS = 6,
CONF_HW_RATE_INDEX_18MBPS = 7,
CONF_HW_RATE_INDEX_24MBPS = 8,
CONF_HW_RATE_INDEX_36MBPS = 9,
CONF_HW_RATE_INDEX_48MBPS = 10,
CONF_HW_RATE_INDEX_54MBPS = 11,
CONF_HW_RATE_INDEX_MCS0 = 12,
CONF_HW_RATE_INDEX_MCS1 = 13,
CONF_HW_RATE_INDEX_MCS2 = 14,
CONF_HW_RATE_INDEX_MCS3 = 15,
CONF_HW_RATE_INDEX_MCS4 = 16,
CONF_HW_RATE_INDEX_MCS5 = 17,
CONF_HW_RATE_INDEX_MCS6 = 18,
CONF_HW_RATE_INDEX_MCS7 = 19,
CONF_HW_RATE_INDEX_MCS7_SGI = 20,
CONF_HW_RATE_INDEX_MCS0_40MHZ = 21,
CONF_HW_RATE_INDEX_MCS1_40MHZ = 22,
CONF_HW_RATE_INDEX_MCS2_40MHZ = 23,
CONF_HW_RATE_INDEX_MCS3_40MHZ = 24,
CONF_HW_RATE_INDEX_MCS4_40MHZ = 25,
CONF_HW_RATE_INDEX_MCS5_40MHZ = 26,
CONF_HW_RATE_INDEX_MCS6_40MHZ = 27,
CONF_HW_RATE_INDEX_MCS7_40MHZ = 28,
CONF_HW_RATE_INDEX_MCS7_40MHZ_SGI = 29,
/* MCS8+ rates overlap with 40Mhz rates */
CONF_HW_RATE_INDEX_MCS8 = 21,
CONF_HW_RATE_INDEX_MCS9 = 22,
CONF_HW_RATE_INDEX_MCS10 = 23,
CONF_HW_RATE_INDEX_MCS11 = 24,
CONF_HW_RATE_INDEX_MCS12 = 25,
CONF_HW_RATE_INDEX_MCS13 = 26,
CONF_HW_RATE_INDEX_MCS14 = 27,
CONF_HW_RATE_INDEX_MCS15 = 28,
CONF_HW_RATE_INDEX_MCS15_SGI = 29,
CONF_HW_RATE_INDEX_MAX = CONF_HW_RATE_INDEX_MCS7_40MHZ_SGI,
};
#define CONF_HW_RXTX_RATE_UNSUPPORTED 0xff
enum {
CONF_SG_DISABLE = 0,
CONF_SG_PROTECTIVE,
CONF_SG_OPPORTUNISTIC
};
#define WLCORE_CONF_SG_PARAMS_MAX 67
#define WLCORE_CONF_SG_PARAMS_ALL 0xff
struct conf_sg_settings {
u32 params[WLCORE_CONF_SG_PARAMS_MAX];
u8 state;
} __packed;
enum conf_rx_queue_type {
CONF_RX_QUEUE_TYPE_LOW_PRIORITY, /* All except the high priority */
CONF_RX_QUEUE_TYPE_HIGH_PRIORITY, /* Management and voice packets */