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|
/*
Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt73usb
Abstract: Data structures and registers for the rt73usb module.
Supported chipsets: rt2571W & rt2671.
*/
#ifndef RT73USB_H
#define RT73USB_H
/*
* RF chip defines.
*/
#define RF5226 0x0001
#define RF2528 0x0002
#define RF5225 0x0003
#define RF2527 0x0004
/*
* Signal information.
* Default offset is required for RSSI <-> dBm conversion.
*/
#define DEFAULT_RSSI_OFFSET 120
/*
* Register layout information.
*/
#define CSR_REG_BASE 0x3000
#define CSR_REG_SIZE 0x04b0
#define EEPROM_BASE 0x0000
#define EEPROM_SIZE 0x0100
#define BBP_BASE 0x0000
#define BBP_SIZE 0x0080
#define RF_BASE 0x0004
#define RF_SIZE 0x0010
/*
* Number of TX queues.
*/
#define NUM_TX_QUEUES 4
/*
* USB registers.
*/
/*
* MCU_LEDCS: LED control for MCU Mailbox.
*/
#define MCU_LEDCS_LED_MODE FIELD16(0x001f)
#define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
#define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
#define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
#define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
#define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
#define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
#define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
#define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
#define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
#define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
#define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
/*
* 8051 firmware image.
*/
#define FIRMWARE_RT2571 "rt73.bin"
#define FIRMWARE_IMAGE_BASE 0x0800
/*
* Security key table memory.
* 16 entries 32-byte for shared key table
* 64 entries 32-byte for pairwise key table
* 64 entries 8-byte for pairwise ta key table
*/
#define SHARED_KEY_TABLE_BASE 0x1000
#define PAIRWISE_KEY_TABLE_BASE 0x1200
#define PAIRWISE_TA_TABLE_BASE 0x1a00
#define SHARED_KEY_ENTRY(__idx) \
( SHARED_KEY_TABLE_BASE + \
((__idx) * sizeof(struct hw_key_entry)) )
#define PAIRWISE_KEY_ENTRY(__idx) \
( PAIRWISE_KEY_TABLE_BASE + \
((__idx) * sizeof(struct hw_key_entry)) )
#define PAIRWISE_TA_ENTRY(__idx) \
( PAIRWISE_TA_TABLE_BASE + \
((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
struct hw_key_entry {
u8 key[16];
u8 tx_mic[8];
u8 rx_mic[8];
} __packed;
struct hw_pairwise_ta_entry {
u8 address[6];
u8 cipher;
u8 reserved;
} __packed;
/*
* Since NULL frame won't be that long (256 byte),
* We steal 16 tail bytes to save debugging settings.
*/
#define HW_DEBUG_SETTING_BASE 0x2bf0
/*
* On-chip BEACON frame space.
*/
#define HW_BEACON_BASE0 0x2400
#define HW_BEACON_BASE1 0x2500
#define HW_BEACON_BASE2 0x2600
#define HW_BEACON_BASE3 0x2700
#define HW_BEACON_OFFSET(__index) \
( HW_BEACON_BASE0 + (__index * 0x0100) )
/*
* MAC Control/Status Registers(CSR).
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* MAC_CSR0: ASIC revision number.
*/
#define MAC_CSR0 0x3000
#define MAC_CSR0_REVISION FIELD32(0x0000000f)
#define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
/*
* MAC_CSR1: System control register.
* SOFT_RESET: Software reset bit, 1: reset, 0: normal.
* BBP_RESET: Hardware reset BBP.
* HOST_READY: Host is ready after initialization, 1: ready.
*/
#define MAC_CSR1 0x3004
#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
#define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
#define MAC_CSR1_HOST_READY FIELD32(0x00000004)
/*
* MAC_CSR2: STA MAC register 0.
*/
#define MAC_CSR2 0x3008
#define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
#define MAC_CSR2_BYTE3 FIELD32(0xff000000)
/*
* MAC_CSR3: STA MAC register 1.
* UNICAST_TO_ME_MASK:
* Used to mask off bits from byte 5 of the MAC address
* to determine the UNICAST_TO_ME bit for RX frames.
* The full mask is complemented by BSS_ID_MASK:
* MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
*/
#define MAC_CSR3 0x300c
#define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
/*
* MAC_CSR4: BSSID register 0.
*/
#define MAC_CSR4 0x3010
#define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
#define MAC_CSR4_BYTE3 FIELD32(0xff000000)
/*
* MAC_CSR5: BSSID register 1.
* BSS_ID_MASK:
* This mask is used to mask off bits 0 and 1 of byte 5 of the
* BSSID. This will make sure that those bits will be ignored
* when determining the MY_BSS of RX frames.
* 0: 1-BSSID mode (BSS index = 0)
* 1: 2-BSSID mode (BSS index: Byte5, bit 0)
* 2: 2-BSSID mode (BSS index: byte5, bit 1)
* 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
*/
#define MAC_CSR5 0x3014
#define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
/*
* MAC_CSR6: Maximum frame length register.
*/
#define MAC_CSR6 0x3018
#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
/*
* MAC_CSR7: Reserved
*/
#define MAC_CSR7 0x301c
/*
* MAC_CSR8: SIFS/EIFS register.
* All units are in US.
*/
#define MAC_CSR8 0x3020
#define MAC_CSR8_SIFS FIELD32(0x000000ff)
#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
#define MAC_CSR8_EIFS FIELD32(0xffff0000)
/*
* MAC_CSR9: Back-Off control register.
* SLOT_TIME: Slot time, default is 20us for 802.11BG.
* CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
* CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
* CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
*/
#define MAC_CSR9 0x3024
#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
#define MAC_CSR9_CWMIN FIELD32(0x00000f00)
#define MAC_CSR9_CWMAX FIELD32(0x0000f000)
#define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
/*
* MAC_CSR10: Power state configuration.
*/
#define MAC_CSR10 0x3028
/*
* MAC_CSR11: Power saving transition time register.
* DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
* TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
* WAKEUP_LATENCY: In unit of TU.
*/
#define MAC_CSR11 0x302c
#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
/*
* MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
* CURRENT_STATE: 0:sleep, 1:awake.
* FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
* BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
*/
#define MAC_CSR12 0x3030
#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
/*
* MAC_CSR13: GPIO.
*/
#define MAC_CSR13 0x3034
#define MAC_CSR13_BIT0 FIELD32(0x00000001)
#define MAC_CSR13_BIT1 FIELD32(0x00000002)
#define MAC_CSR13_BIT2 FIELD32(0x00000004)
#define MAC_CSR13_BIT3 FIELD32(0x00000008)
#define MAC_CSR13_BIT4 FIELD32(0x00000010)
#define MAC_CSR13_BIT5 FIELD32(0x00000020)
#define MAC_CSR13_BIT6 FIELD32(0x00000040)
#define MAC_CSR13_BIT7 FIELD32(0x00000080)
#define MAC_CSR13_BIT8 FIELD32(0x00000100)
#define MAC_CSR13_BIT9 FIELD32(0x00000200)
#define MAC_CSR13_BIT10 FIELD32(0x00000400)
#define MAC_CSR13_BIT11 FIELD32(0x00000800)
#define MAC_CSR13_BIT12 FIELD32(0x00001000)
/*
* MAC_CSR14: LED control register.
* ON_PERIOD: On period, default 70ms.
* OFF_PERIOD: Off period, default 30ms.
* HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
* SW_LED: s/w LED, 1: ON, 0: OFF.
* HW_LED_POLARITY: 0: active low, 1: active high.
*/
#define MAC_CSR14 0x3038
#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
#define MAC_CSR14_HW_LED FIELD32(0x00010000)
#define MAC_CSR14_SW_LED FIELD32(0x00020000)
#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
#define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
/*
* MAC_CSR15: NAV control.
*/
#define MAC_CSR15 0x303c
/*
* TXRX control registers.
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* TXRX_CSR0: TX/RX configuration register.
* TSF_OFFSET: Default is 24.
* AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
* DISABLE_RX: Disable Rx engine.
* DROP_CRC: Drop CRC error.
* DROP_PHYSICAL: Drop physical error.
* DROP_CONTROL: Drop control frame.
* DROP_NOT_TO_ME: Drop not to me unicast frame.
* DROP_TO_DS: Drop fram ToDs bit is true.
* DROP_VERSION_ERROR: Drop version error frame.
* DROP_MULTICAST: Drop multicast frames.
* DROP_BORADCAST: Drop broadcast frames.
* DROP_ACK_CTS: Drop received ACK and CTS.
*/
#define TXRX_CSR0 0x3040
#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
#define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
/*
* TXRX_CSR1
*/
#define TXRX_CSR1 0x3044
#define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
#define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
#define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
#define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
#define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
#define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
#define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
#define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
/*
* TXRX_CSR2
*/
#define TXRX_CSR2 0x3048
#define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
#define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
#define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
#define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
#define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
#define TXRX_CSR2_BB
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