path: root/drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2009-2012  Realtek Corporation.*/

#ifndef __REALTEK_92S_REG_H__
#define __REALTEK_92S_REG_H__

/* 1. System Configuration Registers  */
#define	REG_SYS_ISO_CTRL			0x0000
#define	REG_SYS_FUNC_EN				0x0002
#define	PMC_FSM					0x0004
#define	SYS_CLKR				0x0008
#define	EPROM_CMD				0x000A
#define	EE_VPD					0x000C
#define	AFE_MISC				0x0010
#define	SPS0_CTRL				0x0011
#define	SPS1_CTRL				0x0018
#define	RF_CTRL					0x001F
#define	LDOA15_CTRL				0x0020
#define	LDOV12D_CTRL				0x0021
#define	LDOHCI12_CTRL				0x0022
#define	LDO_USB_SDIO				0x0023
#define	LPLDO_CTRL				0x0024
#define	AFE_XTAL_CTRL				0x0026
#define	AFE_PLL_CTRL				0x0028
#define	REG_EFUSE_CTRL				0x0030
#define	REG_EFUSE_TEST				0x0034
#define	PWR_DATA				0x0038
#define	DBG_PORT				0x003A
#define	DPS_TIMER				0x003C
#define	RCLK_MON				0x003E

/* 2. Command Control Registers	  */
#define	CMDR					0x0040
#define	TXPAUSE					0x0042
#define	LBKMD_SEL				0x0043
#define	TCR					0x0044
#define	RCR					0x0048
#define	MSR					0x004C
#define	SYSF_CFG				0x004D
#define	RX_PKY_LIMIT				0x004E
#define	MBIDCTRL				0x004F

/* 3. MACID Setting Registers	 */
#define	MACIDR					0x0050
#define	MACIDR0					0x0050
#define	MACIDR4					0x0054
#define	BSSIDR					0x0058
#define	HWVID					0x005E
#define	MAR					0x0060
#define	MBIDCAMCONTENT				0x0068
#define	MBIDCAMCFG				0x0070
#define	BUILDTIME				0x0074
#define	BUILDUSER				0x0078

#define	IDR0					MACIDR0
#define	IDR4					MACIDR4

/* 4. Timing Control Registers	 */
#define	TSFR					0x0080
#define	SLOT_TIME				0x0089
#define	USTIME					0x008A
#define	SIFS_CCK				0x008C
#define	SIFS_OFDM				0x008E
#define	PIFS_TIME				0x0090
#define	ACK_TIMEOUT				0x0091
#define	EIFSTR					0x0092
#define	BCN_INTERVAL				0x0094
#define	ATIMWND					0x0096
#define	BCN_DRV_EARLY_INT			0x0098
#define	BCN_DMATIME				0x009A
#define	BCN_ERR_THRESH				0x009C
#define	MLT					0x009D
#define	RSVD_MAC_TUNE_US			0x009E

/* 5. FIFO Control Registers	  */
#define RQPN					0x00A0
#define	RQPN1					0x00A0
#define	RQPN2					0x00A1
#define	RQPN3					0x00A2
#define	RQPN4					0x00A3
#define	RQPN5					0x00A4
#define	RQPN6					0x00A5
#define	RQPN7					0x00A6
#define	RQPN8					0x00A7
#define	RQPN9					0x00A8
#define	RQPN10					0x00A9
#define	LD_RQPN					0x00AB
#define	RXFF_BNDY				0x00AC
#define	RXRPT_BNDY				0x00B0
#define	TXPKTBUF_PGBNDY				0x00B4
#define	PBP					0x00B5
#define	RXDRVINFO_SZ				0x00B6
#define	TXFF_STATUS				0x00B7
#define	RXFF_STATUS				0x00B8
#define	TXFF_EMPTY_TH				0x00B9
#define	SDIO_RX_BLKSZ				0x00BC
#define	RXDMA					0x00BD
#define	RXPKT_NUM				0x00BE
#define	C2HCMD_UDT_SIZE				0x00C0
#define	C2HCMD_UDT_ADDR				0x00C2
#define	FIFOPAGE1				0x00C4
#define	FIFOPAGE2				0x00C8
#define	FIFOPAGE3				0x00CC
#define	FIFOPAGE4				0x00D0
#define	FIFOPAGE5				0x00D4
#define	FW_RSVD_PG_CRTL				0x00D8
#define	RXDMA_AGG_PG_TH				0x00D9
#define	TXDESC_MSK				0x00DC
#define	TXRPTFF_RDPTR				0x00E0
#define	TXRPTFF_WTPTR				0x00E4
#define	C2HFF_RDPTR				0x00E8
#define	C2HFF_WTPTR				0x00EC
#define	RXFF0_RDPTR				0x00F0
#define	RXFF0_WTPTR				0x00F4
#define	RXFF1_RDPTR				0x00F8
#define	RXFF1_WTPTR				0x00FC
#define	RXRPT0_RDPTR				0x0100
#define	RXRPT0_WTPTR				0x0104
#define	RXRPT1_RDPTR				0x0108
#define	RXRPT1_WTPTR				0x010C
#define	RX0_UDT_SIZE				0x0110
#define	RX1PKTNUM				0x0114
#define	RXFILTERMAP				0x0116
#define	RXFILTERMAP_GP1				0x0118
#define	RXFILTERMAP_GP2				0x011A
#define	RXFILTERMAP_GP3				0x011C
#define	BCNQ_CTRL				0x0120
#define	MGTQ_CTRL				0x0124
#define	HIQ_CTRL				0x0128
#define	VOTID7_CTRL				0x012c
#define	VOTID6_CTRL				0x0130
#define	VITID5_CTRL				0x0134
#define	VITID4_CTRL				0x0138
#define	BETID3_CTRL				0x013c
#define	BETID0_CTRL				0x0140
#define	BKTID2_CTRL				0x0144
#define	BKTID1_CTRL				0x0148
#define	CMDQ_CTRL				0x014c
#define	TXPKT_NUM_CTRL				0x0150
#define	TXQ_PGADD				0x0152
#define	TXFF_PG_NUM				0x0154
#define	TRXDMA_STATUS				0x0156

/* 6. Adaptive Control Registers   */
#define	INIMCS_SEL				0x0160
#define	TX_RATE_REG				INIMCS_SEL
#define	INIRTSMCS_SEL				0x0180
#define	RRSR					0x0181
#define	ARFR0					0x0184
#define	ARFR1					0x0188
#define	ARFR2					0x018C
#define	ARFR3					0x0190
#define	ARFR4					0x0194
#define	ARFR5					0x0198
#define	ARFR6					0x019C
#define	ARFR7					0x01A0
#define	AGGLEN_LMT_H				0x01A7
#define	AGGLEN_LMT_L				0x01A8
#define	DARFRC					0x01B0
#define	RARFRC					0x01B8
#define	MCS_TXAGC				0x01C0
#define	CCK_TXAGC				0x01C8

/* 7. EDCA Setting Registers */
#define	EDCAPARA_VO				0x01D0
#define	EDCAPARA_VI				0x01D4
#define	EDCAPARA_BE				0x01D8
#define	EDCAPARA_BK				0x01DC
#define	BCNTCFG					0x01E0
#define	CWRR					0x01E2
#define	ACMAVG					0x01E4
#define	ACMHWCTRL				0x01E7
#define	VO_ADMTM				0x01E8
#define	VI_ADMTM				0x01EC
#define	BE_ADMTM				0x01F0
#define	RETRY_LIMIT				0x01F4
#define	SG_RATE					0x01F6

/* 8. WMAC, BA and CCX related Register. */
#define	NAV_CTRL				0x0200
#define	BW_OPMODE				0x0203
#define	BACAMCMD				0x0204
#define	BACAMCONTENT				0x0208

/* the 0x2xx register WMAC definition */
#define	LBDLY					0x0210
#define	FWDLY					0x0211
#define	HWPC_RX_CTRL				0x0218
#define	MQIR					0x0220
#define	MAIR					0x0222
#define	MSIR					0x0224
#define	CLM_RESULT				0x0227
#define	NHM_RPI_CNT				0x0228
#define	RXERR_RPT				0x0230
#define	NAV_PROT_LEN				0x0234
#define	CFEND_TH				0x0236
#define	AMPDU_MIN_SPACE				0x0237
#define	TXOP_STALL_CTRL				0x0238

/* 9. Security Control Registers */
#define	REG_RWCAM				0x0240
#define	REG_WCAMI				0x0244
#define	REG_RCAMO				0x0248
#define	REG_CAMDBG				0x024C
#define	REG_SECR				0x0250

/* 10. Power Save Control Registers */
#define	WOW_CTRL				0x0260
#define	PSSTATUS				0x0261
#define	PSSWITCH				0x0262
#define	MIMOPS_WAIT_PERIOD			0x0263
#define	LPNAV_CTRL				0x0264
#define	WFM0					0x0270
#define	WFM1					0x0280
#define	WFM2					0x0290
#define	WFM3					0x02A0
#define	WFM4					0x02B0
#define	WFM5					0x02C0
#define	WFCRC					0x02D0
#define	FW_RPT_REG				0x02c4

/* 11. General Purpose Registers */
#define	PSTIME					0x02E0
#define	TIMER0					0x02E4
#define	TIMER1					0x02E8
#define	GPIO_IN_SE				0x02EC
#define	GPIO_IO_SEL				0x02EE
#define	MAC_PINMUX_CFG				0x02F1
#define	LEDCFG					0x02F2
#define	PHY_REG					0x02F3
#define	PHY_REG_DATA				0x02F4
#define	REG_EFUSE_CLK				0x02F8

/* 12. Host Interrupt Status Registers */
#define	INTA_MASK				0x0300
#define	ISR					0x0308

/* 13. Test mode and Debug Control Registers */
#define	DBG_PORT_SWITCH				0x003A
#define	BIST					0x0310
#define	DBS					0x0314
#define	CPUINST					0x0318
#define	CPUCAUSE				0x031C
#define	LBUS_ERR_ADDR				0x0320
#define	LBUS_ERR_CMD				0x0324
#define	LBUS_ERR_DATA_L				0x0328
#define	LBUS_ERR_DATA_H				0x032C
#define	LX_EXCEPTION_ADDR			0x0330
#define	WDG_CTRL				0x0334
#define	INTMTU					0x0338
#define	INTM					0x033A
#define	FDLOCKTURN0				0x033C
#define	FDLOCKTURN1				0x033D
#define	TRXPKTBUF_DBG_DATA			0x0340
#define	TRXPKTBUF_DBG_CTRL			0x0348
#define	DPLL					0x034A
#define	CBUS_ERR_ADDR				0x0350
#define	CBUS_ERR_CMD				0x0354
#define	CBUS_ERR_DATA_L				0x0358
#define	CBUS_ERR_DATA_H				0x035C
#define	USB_SIE_INTF_ADDR			0x0360
#define	USB_SIE_INTF_WD				0x0361
#define	USB_SIE_INTF_RD				0x0362
#define	USB_SIE_INTF_CTRL			0x0363
#define LBUS_MON_ADDR				0x0364
#define LBUS_ADDR_MASK				0x0368

/* Boundary is 0x37F */

/* 14. PCIE config register */
#define	TP_POLL					0x0500
#define	PM_CTRL					0x0502
#define	PCIF					0x0503

#define	THPDA					0x0514
#define	TMDA					0x0518
#define	TCDA					0x051C
#define	HDA					0x0520
#define	TVODA					0x0524
#define	TVIDA					0x0528
#define	TBEDA					0x052C
#define	TBKDA					0x0530
#define	TBDA					0x0534
#define	RCDA					0x0538
#define	RDQDA					0x053C
#define	DBI_WDATA				0x0540
#define	DBI_RDATA				0x0544
#define	DBI_CTRL				0x0548
#define	MDIO_DATA				0x0550
#define	MDIO_CTRL				0x0554
#define	PCI_RPWM				0x0561
#define	PCI_CPWM				0x0563

/* Config register	(Offset 0x800-) */
#define	PHY_CCA					0x803

/* Min Spacing related settings. */
#define	MAX_MSS_DENSITY_2T			0x13
#define	MAX_MSS_DENSITY_1T			0x0A

/* Rx DMA Control related settings */
#define	RXDMA_AGG_EN				BIT(7)

#define	RPWM					PCI_RPWM

/* Regsiter Bit and Content definition  */

#define	ISO_MD2PP				BIT(0)
#define	ISO_PA2PCIE				BIT(3)
#define	ISO_PLL2MD				BIT(4)
#define	ISO_PWC_DV2RP				BIT(11)
#define	ISO_PWC_RV2RP				BIT(12)


#define	FEN_MREGEN				BIT(15)
#define	FEN_DCORE				BIT(11)
#define	FEN_CPUEN				BIT(10)

#define	PAD_HWPD_IDN				BIT(22)

#define	SYS_CLKSEL_80M				BIT(0)
#define	SYS_PS_CLKSEL				BIT(1)
#define	SYS_CPU_CLKSEL				BIT(2)
#define	SYS_MAC_CLK_EN				BIT(11)
#define	SYS_SWHW_SEL				BIT(14)
#define	SYS_FWHW_SEL				BIT(15)

#define	CMDEEPROM_EN				BIT(5)
#define	CMDEERPOMSEL				BIT(4)
#define	CMD9346CR_9356SEL			BIT(4)

#define	AFE_MBEN				BIT(1)
#define	AFE_BGEN				BIT(0)

#define	SPS1_SWEN				BIT(1)
#define	SPS1_LDEN				BIT(0)

#define	RF_EN					BIT(0)
#define	RF_RSTB					BIT(1)
#define	RF_SDMRSTB				BIT(2)

#define	LDA15_EN				BIT(0)

#define	LDV12_EN				BIT(0)
#define	LDV12_SDBY				BIT(1)

#define	XTAL_GATE_AFE				BIT(10)

#define	APLL_EN					BIT(0)

#define	AFR_CARDBEN				BIT(0)
#define	AFR_CLKRUN_SEL				BIT(1)
#define	AFR_FUNCREGEN				BIT(2)

#define	APSDOFF_STATUS				BIT(15)
#define	APSDOFF					BIT(14)
#define	BBRSTN					BIT(13)
#de