path: root/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
 *
 * Register definitions taken from original Realtek rtl8723au driver
 */

/* 0x0000 ~ 0x00FF	System Configuration */
#define REG_SYS_ISO_CTRL		0x0000
#define  SYS_ISO_MD2PP			BIT(0)
#define  SYS_ISO_ANALOG_IPS		BIT(5)
#define  SYS_ISO_DIOR			BIT(9)
#define  SYS_ISO_PWC_EV25V		BIT(14)
#define  SYS_ISO_PWC_EV12V		BIT(15)

#define REG_SYS_FUNC			0x0002
#define  SYS_FUNC_BBRSTB		BIT(0)
#define  SYS_FUNC_BB_GLB_RSTN		BIT(1)
#define  SYS_FUNC_USBA			BIT(2)
#define  SYS_FUNC_UPLL			BIT(3)
#define  SYS_FUNC_USBD			BIT(4)
#define  SYS_FUNC_DIO_PCIE		BIT(5)
#define  SYS_FUNC_PCIEA			BIT(6)
#define  SYS_FUNC_PPLL			BIT(7)
#define  SYS_FUNC_PCIED			BIT(8)
#define  SYS_FUNC_DIOE			BIT(9)
#define  SYS_FUNC_CPU_ENABLE		BIT(10)
#define  SYS_FUNC_DCORE			BIT(11)
#define  SYS_FUNC_ELDR			BIT(12)
#define  SYS_FUNC_DIO_RF		BIT(13)
#define  SYS_FUNC_HWPDN			BIT(14)
#define  SYS_FUNC_MREGEN		BIT(15)

#define REG_APS_FSMCO			0x0004
#define  APS_FSMCO_PFM_ALDN		BIT(1)
#define  APS_FSMCO_PFM_WOWL		BIT(3)
#define  APS_FSMCO_ENABLE_POWERDOWN	BIT(4)
#define  APS_FSMCO_MAC_ENABLE		BIT(8)
#define  APS_FSMCO_MAC_OFF		BIT(9)
#define  APS_FSMCO_SW_LPS		BIT(10)
#define  APS_FSMCO_HW_SUSPEND		BIT(11)
#define  APS_FSMCO_PCIE			BIT(12)
#define  APS_FSMCO_HW_POWERDOWN		BIT(15)
#define  APS_FSMCO_WLON_RESET		BIT(16)

#define REG_SYS_CLKR			0x0008
#define  SYS_CLK_ANAD16V_ENABLE		BIT(0)
#define  SYS_CLK_ANA8M			BIT(1)
#define  SYS_CLK_MACSLP			BIT(4)
#define  SYS_CLK_LOADER_ENABLE		BIT(5)
#define  SYS_CLK_80M_SSC_DISABLE	BIT(7)
#define  SYS_CLK_80M_SSC_ENABLE_HO	BIT(8)
#define  SYS_CLK_PHY_SSC_RSTB		BIT(9)
#define  SYS_CLK_SEC_CLK_ENABLE		BIT(10)
#define  SYS_CLK_MAC_CLK_ENABLE		BIT(11)
#define  SYS_CLK_ENABLE			BIT(12)
#define  SYS_CLK_RING_CLK_ENABLE	BIT(13)

#define REG_9346CR			0x000a
#define  EEPROM_BOOT			BIT(4)
#define  EEPROM_ENABLE			BIT(5)

#define REG_EE_VPD			0x000c
#define REG_AFE_MISC			0x0010
#define  AFE_MISC_WL_XTAL_CTRL		BIT(6)

#define REG_SPS0_CTRL			0x0011
#define REG_SPS_OCP_CFG			0x0018
#define REG_8192E_LDOV12_CTRL		0x0014
#define REG_RSV_CTRL			0x001c

#define REG_RF_CTRL			0x001f
#define  RF_ENABLE			BIT(0)
#define  RF_RSTB			BIT(1)
#define  RF_SDMRSTB			BIT(2)

#define REG_LDOA15_CTRL			0x0020
#define  LDOA15_ENABLE			BIT(0)
#define  LDOA15_STANDBY			BIT(1)
#define  LDOA15_OBUF			BIT(2)
#define  LDOA15_REG_VOS			BIT(3)
#define  LDOA15_VOADJ_SHIFT		4

#define REG_LDOV12D_CTRL		0x0021
#define  LDOV12D_ENABLE			BIT(0)
#define  LDOV12D_STANDBY		BIT(1)
#define  LDOV12D_VADJ_SHIFT		4

#define REG_LDOHCI12_CTRL		0x0022

#define REG_LPLDO_CTRL			0x0023
#define  LPLDO_HSM			BIT(2)
#define  LPLDO_LSM_DIS			BIT(3)

#define REG_AFE_XTAL_CTRL		0x0024
#define  AFE_XTAL_ENABLE		BIT(0)
#define  AFE_XTAL_B_SELECT		BIT(1)
#define  AFE_XTAL_GATE_USB		BIT(8)
#define  AFE_XTAL_GATE_AFE		BIT(11)
#define  AFE_XTAL_RF_GATE		BIT(14)
#define  AFE_XTAL_GATE_DIG		BIT(17)
#define  AFE_XTAL_BT_GATE		BIT(20)

/*
 * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu
 */
#define REG_AFE_PLL_CTRL		0x0028
#define  AFE_PLL_ENABLE			BIT(0)
#define  AFE_PLL_320_ENABLE		BIT(1)
#define  APE_PLL_FREF_SELECT		BIT(2)
#define  AFE_PLL_EDGE_SELECT		BIT(3)
#define  AFE_PLL_WDOGB			BIT(4)
#define  AFE_PLL_LPF_ENABLE		BIT(5)

#define REG_MAC_PHY_CTRL		0x002c

#define REG_EFUSE_CTRL			0x0030
#define REG_EFUSE_TEST			0x0034
#define  EFUSE_TRPT			BIT(7)
	/*  00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
#define  EFUSE_CELL_SEL			(BIT(8) | BIT(9))
#define  EFUSE_LDOE25_ENABLE		BIT(31)
#define  EFUSE_SELECT_MASK		0x0300
#define  EFUSE_WIFI_SELECT		0x0000
#define  EFUSE_BT0_SELECT		0x0100
#define  EFUSE_BT1_SELECT		0x0200
#define  EFUSE_BT2_SELECT		0x0300

#define  EFUSE_ACCESS_ENABLE		0x69	/* RTL8723 only */
#define  EFUSE_ACCESS_DISABLE		0x00	/* RTL8723 only */

#define REG_PWR_DATA			0x0038
#define  PWR_DATA_EEPRPAD_RFE_CTRL_EN	BIT(11)

#define REG_CAL_TIMER			0x003c
#define REG_ACLK_MON			0x003e
#define REG_GPIO_MUXCFG			0x0040
#define REG_GPIO_IO_SEL			0x0042
#define REG_MAC_PINMUX_CFG		0x0043
#define REG_GPIO_PIN_CTRL		0x0044
#define REG_GPIO_INTM			0x0048
#define  GPIO_INTM_EDGE_TRIG_IRQ	BIT(9)

#define REG_LEDCFG0			0x004c
#define  LEDCFG0_DPDT_SELECT		BIT(23)
#define REG_LEDCFG1			0x004d
#define REG_LEDCFG2			0x004e
#define  LEDCFG2_DPDT_SELECT		BIT(7)
#define REG_LEDCFG3			0x004f
#define REG_LEDCFG			REG_LEDCFG2
#define REG_FSIMR			0x0050
#define REG_FSISR			0x0054
#define REG_HSIMR			0x0058
#define REG_HSISR			0x005c
/*  RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
#define REG_GPIO_PIN_CTRL_2		0x0060
/*  RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
#define REG_GPIO_IO_SEL_2		0x0062
#define  GPIO_IO_SEL_2_GPIO09_INPUT	BIT(1)
#define  GPIO_IO_SEL_2_GPIO09_IRQ	BIT(9)

/*  RTL8723B */
#define REG_PAD_CTRL1			0x0064
#define  PAD_CTRL1_SW_DPDT_SEL_DATA	BIT(0)

/*  RTL8723 only WIFI/BT/GPS Multi-Function control source. */
#define REG_MULTI_FUNC_CTRL		0x0068

#define  MULTI_FN_WIFI_HW_PWRDOWN_EN	BIT(0)	/* Enable GPIO[9] as WiFi HW
						   powerdown source */
#define  MULTI_FN_WIFI_HW_PWRDOWN_SL	BIT(1)	/* WiFi HW powerdown polarity
						   control */
#define  MULTI_WIFI_FUNC_EN		BIT(2)	/* WiFi function enable */

#define  MULTI_WIFI_HW_ROF_EN		BIT(3)	/* Enable GPIO[9] as WiFi RF HW
						   powerdown source */
#define  MULTI_BT_HW_PWRDOWN_EN		BIT(16)	/* Enable GPIO[11] as BT HW
						   powerdown source */
#define  MULTI_BT_HW_PWRDOWN_SL		BIT(17)	/* BT HW powerdown polarity
						   control */
#define  MULTI_BT_FUNC_EN		BIT(18)	/* BT function enable */
#define  MULTI_BT_HW_ROF_EN		BIT(19)	/* Enable GPIO[11] as BT/GPS
						   RF HW powerdown source */
#define  MULTI_GPS_HW_PWRDOWN_EN	BIT(20)	/* Enable GPIO[10] as GPS HW
						   powerdown source */
#define  MULTI_GPS_HW_PWRDOWN_SL	BIT(21)	/* GPS HW powerdown polarity
						   control */
#define  MULTI_GPS_FUNC_EN		BIT(22)	/* GPS function enable */

#define REG_AFE_CTRL4			0x0078	/* 8192eu/8723bu */
#define REG_LDO_SW_CTRL			0x007c	/* 8192eu */

#define REG_MCU_FW_DL			0x0080
#define  MCU_FW_DL_ENABLE		BIT(0)
#define  MCU_FW_DL_READY		BIT(1)
#define  MCU_FW_DL_CSUM_REPORT		BIT(2)
#define  MCU_MAC_INIT_READY		BIT(3)
#define  MCU_BB_INIT_READY		BIT(4)
#define  MCU_RF_INIT_READY		BIT(5)
#define  MCU_WINT_INIT_READY		BIT(6)
#define  MCU_FW_RAM_SEL			BIT(7)	/* 1: RAM, 0:ROM */
#define  MCU_CP_RESET			BIT(23)

#define REG_HMBOX_EXT_0			0x0088
#define REG_HMBOX_EXT_1			0x008a
#define REG_HMBOX_EXT_2			0x008c
#define REG_HMBOX_EXT_3			0x008e

/* Interrupt registers for 8192e/8723bu/8812 */
#define REG_HIMR0			0x00b0
#define	 IMR0_TXCCK			BIT(30)	/* TXRPT interrupt when CCX bit
						   of the packet is set */
#define	 IMR0_PSTIMEOUT			BIT(29)	/* Power Save Time Out Int */
#define	 IMR0_GTINT4			BIT(28)	/* Set when GTIMER4 expires */
#define	 IMR0_GTINT3			BIT(27)	/* Set when GTIMER3 expires */
#define	 IMR0_TBDER			BIT(26)	/* Transmit Beacon0 Error */
#define	 IMR0_TBDOK			BIT(25)	/* Transmit Beacon0 OK */
#define	 IMR0_TSF_BIT32_TOGGLE		BIT(24)	/* TSF Timer BIT32 toggle
						   indication interrupt */
#define	 IMR0_BCNDMAINT0		BIT(20)	/* Beacon DMA Interrupt 0 */
#define	 IMR0_BCNDERR0			BIT(16)	/* Beacon Queue DMA Error 0 */
#define	 IMR0_HSISR_IND_ON_INT		BIT(15)	/* HSISR Indicator (HSIMR &
						   HSISR is true) */
#define	 IMR0_BCNDMAINT_E		BIT(14)	/* Beacon DMA Interrupt
						   Extension for Win7 */
#define	 IMR0_ATIMEND			BIT(12)	/* CTWidnow End or
						   ATIM Window End */
#define	 IMR0_HISR1_IND_INT		BIT(11)	/* HISR1 Indicator
						   (HISR1 & HIMR1 is true) */
#define	 IMR0_C2HCMD			BIT(10)	/* CPU to Host Command INT
						   Status, Write 1 to clear */
#define	 IMR0_CPWM2			BIT(9)	/* CPU power Mode exchange INT
						   Status, Write 1 to clear */
#define	 IMR0_CPWM			BIT(8)	/* CPU power Mode exchange INT
						   Status, Write 1 to clear */
#define	 IMR0_HIGHDOK			BIT(7)	/* High Queue DMA OK */
#define	 IMR0_MGNTDOK			BIT(6)	/* Management Queue DMA OK */
#define	 IMR0_BKDOK			BIT(5)	/* AC_BK DMA OK */
#define	 IMR0_BEDOK			BIT(4)	/* AC_BE DMA OK */
#define	 IMR0_VIDOK			BIT(3)	/* AC_VI DMA OK */
#define	 IMR0_VODOK			BIT(2)	/* AC_VO DMA OK */
#define	 IMR0_RDU			BIT(1)	/* Rx Descriptor Unavailable */
#define	 IMR0_ROK			BIT(0)	/* Receive DMA OK */
#define REG_HISR0			0x00b4
#define REG_HIMR1			0x00b8
#define	 IMR1_BCNDMAINT7		BIT(27)	/* Beacon DMA Interrupt 7 */
#define	 IMR1_BCNDMAINT6		BIT(26)