path: root/drivers/net/wireless/ralink/rt2x00/rt2500pci.h

/*
	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

/*
	Module: rt2500pci
	Abstract: Data structures and registers for the rt2500pci module.
	Supported chipsets: RT2560.
 */

#ifndef RT2500PCI_H
#define RT2500PCI_H

/*
 * RF chip defines.
 */
#define RF2522				0x0000
#define RF2523				0x0001
#define RF2524				0x0002
#define RF2525				0x0003
#define RF2525E				0x0004
#define RF5222				0x0010

/*
 * RT2560 version
 */
#define RT2560_VERSION_B		2
#define RT2560_VERSION_C		3
#define RT2560_VERSION_D		4

/*
 * Signal information.
 * Default offset is required for RSSI <-> dBm conversion.
 */
#define DEFAULT_RSSI_OFFSET		121

/*
 * Register layout information.
 */
#define CSR_REG_BASE			0x0000
#define CSR_REG_SIZE			0x0174
#define EEPROM_BASE			0x0000
#define EEPROM_SIZE			0x0200
#define BBP_BASE			0x0000
#define BBP_SIZE			0x0040
#define RF_BASE				0x0004
#define RF_SIZE				0x0010

/*
 * Number of TX queues.
 */
#define NUM_TX_QUEUES			2

/*
 * Control/Status Registers(CSR).
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * CSR0: ASIC revision number.
 */
#define CSR0				0x0000
#define CSR0_REVISION			FIELD32(0x0000ffff)

/*
 * CSR1: System control register.
 * SOFT_RESET: Software reset, 1: reset, 0: normal.
 * BBP_RESET: Hardware reset, 1: reset, 0, release.
 * HOST_READY: Host ready after initialization.
 */
#define CSR1				0x0004
#define CSR1_SOFT_RESET			FIELD32(0x00000001)
#define CSR1_BBP_RESET			FIELD32(0x00000002)
#define CSR1_HOST_READY			FIELD32(0x00000004)

/*
 * CSR2: System admin status register (invalid).
 */
#define CSR2				0x0008

/*
 * CSR3: STA MAC address register 0.
 */
#define CSR3				0x000c
#define CSR3_BYTE0			FIELD32(0x000000ff)
#define CSR3_BYTE1			FIELD32(0x0000ff00)
#define CSR3_BYTE2			FIELD32(0x00ff0000)
#define CSR3_BYTE3			FIELD32(0xff000000)

/*
 * CSR4: STA MAC address register 1.
 */
#define CSR4				0x0010
#define CSR4_BYTE4			FIELD32(0x000000ff)
#define CSR4_BYTE5			FIELD32(0x0000ff00)

/*
 * CSR5: BSSID register 0.
 */
#define CSR5				0x0014
#define CSR5_BYTE0			FIELD32(0x000000ff)
#define CSR5_BYTE1			FIELD32(0x0000ff00)
#define CSR5_BYTE2			FIELD32(0x00ff0000)
#define CSR5_BYTE3			FIELD32(0xff000000)

/*
 * CSR6: BSSID register 1.
 */
#define CSR6				0x0018
#define CSR6_BYTE4			FIELD32(0x000000ff)
#define CSR6_BYTE5			FIELD32(0x0000ff00)

/*
 * CSR7: Interrupt source register.
 * Write 1 to clear.
 * TBCN_EXPIRE: Beacon timer expired interrupt.
 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
 * TXDONE_TXRING: Tx ring transmit done interrupt.
 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
 * TXDONE_PRIORING: Priority ring transmit done interrupt.
 * RXDONE: Receive done interrupt.
 * DECRYPTION_DONE: Decryption done interrupt.
 * ENCRYPTION_DONE: Encryption done interrupt.
 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
 * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).

 */
#define CSR7				0x001c
#define CSR7_TBCN_EXPIRE		FIELD32(0x00000001)
#define CSR7_TWAKE_EXPIRE		FIELD32(0x00000002)
#define CSR7_TATIMW_EXPIRE		FIELD32(0x00000004)
#define CSR7_TXDONE_TXRING		FIELD32(0x00000008)
#define CSR7_TXDONE_ATIMRING		FIELD32(0x00000010)
#define CSR7_TXDONE_PRIORING		FIELD32(0x00000020)
#define CSR7_RXDONE			FIELD32(0x00000040)
#define CSR7_DECRYPTION_DONE		FIELD32(0x00000080)
#define CSR7_ENCRYPTION_DONE		FIELD32(0x00000100)
#define CSR7_UART1_TX_TRESHOLD		FIELD32(0x00000200)
#define CSR7_UART1_RX_TRESHOLD		FIELD32(0x00000400)
#define CSR7_UART1_IDLE_TRESHOLD	FIELD32(0x00000800)
#define CSR7_UART1_TX_BUFF_ERROR	FIELD32(0x00001000)
#define CSR7_UART1_RX_BUFF_ERROR	FIELD32(0x00002000)
#define CSR7_UART2_TX_TRESHOLD		FIELD32(0x00004000)
#define CSR7_UART2_RX_TRESHOLD		FIELD32(0x00008000)
#define CSR7_UART2_IDLE_TRESHOLD	FIELD32(0x00010000)
#define CSR7_UART2_TX_BUFF_ERROR	FIELD32(0x00020000)
#define CSR7_UART2_RX_BUFF_ERROR	FIELD32(0x00040000)
#define CSR7_TIMER_CSR3_EXPIRE		FIELD32(0x00080000)

/*
 * CSR8: Interrupt mask register.
 * Write 1 to mask interrupt.
 * TBCN_EXPIRE: Beacon timer expired interrupt.
 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
 * TXDONE_TXRING: Tx ring transmit done interrupt.
 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
 * TXDONE_PRIORING: Priority ring transmit done interrupt.
 * RXDONE: Receive done interrupt.
 * DECRYPTION_DONE: Decryption done interrupt.
 * ENCRYPTION_DONE: Encryption done interrupt.
 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
 * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
 */
#define CSR8				0x0020
#define CSR8_TBCN_EXPIRE		FIELD32(0x00000001)
#define CSR8_TWAKE_EXPIRE		FIELD32(0x00000002)
#define CSR8_TATIMW_EXPIRE		FIELD32(0x00000004)
#define CSR8_TXDONE_TXRING		FIELD32(0x00000008)
#define CSR8_TXDONE_ATIMRING		FIELD32(0x00000010)
#define CSR8_TXDONE_PRIORING		FIELD32(0x00000020)
#define CSR8_RXDONE			FIELD32(0x00000040)
#define CSR8_DECRYPTION_DONE		FIELD32(0x00000080)
#define CSR8_ENCRYPTION_DONE		FIELD32(0x00000100)
#define CSR8_UART1_TX_TRESHOLD		FIELD32(0x00000200)
#define CSR8_UART1_RX_TRESHOLD		FIELD32(0x00000400)
#define CSR8_UART1_IDLE_TRESHOLD	FIELD32(0x00000800)
#define CSR8_UART1_TX_BUFF_ERROR	FIELD32(0x00001000)
#define CSR8_UART1_RX_BUFF_ERROR	FIELD32(0x00002000)
#define CSR8_UART2_TX_TRESHOLD		FIELD32(0x00004000)
#define CSR8_UART2_RX_TRESHOLD		FIELD32(0x00008000)
#define CSR8_UART2_IDLE_TRESHOLD	FIELD32(0x00010000)
#define CSR8_UART2_TX_BUFF_ERROR	FIELD32(0x00020000)
#define CSR8_UART2_RX_BUFF_ERROR	FIELD32(0x00040000)
#define CSR8_TIMER_CSR3_EXPIRE		FIELD32(0x00080000)

/*
 * CSR9: Maximum frame length register.
 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
 */
#define CSR9				0x0024
#define CSR9_MAX_FRAME_UNIT		FIELD32(0x00000f80)

/*
 * SECCSR0: WEP control register.
 * KICK_DECRYPT: Kick decryption engine, self-clear.
 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
 * DESC_ADDRESS: Descriptor physical address of frame.
 */
#define SECCSR0				0x0028
#define SECCSR0_KICK_DECRYPT		FIELD32(0x00000001)
#define SECCSR0_ONE_SHOT		FIELD32(0x00000002)
#define SECCSR0_DESC_ADDRESS		FIELD32(0xfffffffc)

/*
 * CSR11: Back-off control register.
 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
 * SLOT_TIME: Slot time, default is 20us for 802.11b
 * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
 * LONG_RETRY: Long retry count.
 * SHORT_RETRY: Short retry count.
 */
#define CSR11				0x002c
#define CSR11_CWMIN			FIELD32(0x0000000f)
#define CSR11_CWMAX			FIELD32(0x000000f0)
#define CSR11_SLOT_TIME			FIELD32(0x00001f00)
#define CSR11_CW_SELECT			FIELD32(0x00002000)
#define CS