path: root/drivers/net/wireless/b43/b43.h

#ifndef B43_H_
#define B43_H_

#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/hw_random.h>
#include <linux/bcma/bcma.h>
#include <linux/ssb/ssb.h>
#include <linux/completion.h>
#include <net/mac80211.h>

#include "debugfs.h"
#include "leds.h"
#include "rfkill.h"
#include "bus.h"
#include "lo.h"
#include "phy_common.h"


#ifdef CONFIG_B43_DEBUG
# define B43_DEBUG	1
#else
# define B43_DEBUG	0
#endif

/* MMIO offsets */
#define B43_MMIO_DMA0_REASON		0x20
#define B43_MMIO_DMA0_IRQ_MASK		0x24
#define B43_MMIO_DMA1_REASON		0x28
#define B43_MMIO_DMA1_IRQ_MASK		0x2C
#define B43_MMIO_DMA2_REASON		0x30
#define B43_MMIO_DMA2_IRQ_MASK		0x34
#define B43_MMIO_DMA3_REASON		0x38
#define B43_MMIO_DMA3_IRQ_MASK		0x3C
#define B43_MMIO_DMA4_REASON		0x40
#define B43_MMIO_DMA4_IRQ_MASK		0x44
#define B43_MMIO_DMA5_REASON		0x48
#define B43_MMIO_DMA5_IRQ_MASK		0x4C
#define B43_MMIO_MACCTL			0x120	/* MAC control */
#define B43_MMIO_MACCMD			0x124	/* MAC command */
#define B43_MMIO_GEN_IRQ_REASON		0x128
#define B43_MMIO_GEN_IRQ_MASK		0x12C
#define B43_MMIO_RAM_CONTROL		0x130
#define B43_MMIO_RAM_DATA		0x134
#define B43_MMIO_PS_STATUS		0x140
#define B43_MMIO_RADIO_HWENABLED_HI	0x158
#define B43_MMIO_MAC_HW_CAP		0x15C	/* MAC capabilities (corerev >= 13) */
#define B43_MMIO_SHM_CONTROL		0x160
#define B43_MMIO_SHM_DATA		0x164
#define B43_MMIO_SHM_DATA_UNALIGNED	0x166
#define B43_MMIO_XMITSTAT_0		0x170
#define B43_MMIO_XMITSTAT_1		0x174
#define B43_MMIO_REV3PLUS_TSF_LOW	0x180	/* core rev >= 3 only */
#define B43_MMIO_REV3PLUS_TSF_HIGH	0x184	/* core rev >= 3 only */
#define B43_MMIO_TSF_CFP_REP		0x188
#define B43_MMIO_TSF_CFP_START		0x18C
#define B43_MMIO_TSF_CFP_MAXDUR		0x190

/* 32-bit DMA */
#define B43_MMIO_DMA32_BASE0		0x200
#define B43_MMIO_DMA32_BASE1		0x220
#define B43_MMIO_DMA32_BASE2		0x240
#define B43_MMIO_DMA32_BASE3		0x260
#define B43_MMIO_DMA32_BASE4		0x280
#define B43_MMIO_DMA32_BASE5		0x2A0
/* 64-bit DMA */
#define B43_MMIO_DMA64_BASE0		0x200
#define B43_MMIO_DMA64_BASE1		0x240
#define B43_MMIO_DMA64_BASE2		0x280
#define B43_MMIO_DMA64_BASE3		0x2C0
#define B43_MMIO_DMA64_BASE4		0x300
#define B43_MMIO_DMA64_BASE5		0x340

/* PIO on core rev < 11 */
#define B43_MMIO_PIO_BASE0		0x300
#define B43_MMIO_PIO_BASE1		0x310
#define B43_MMIO_PIO_BASE2		0x320
#define B43_MMIO_PIO_BASE3		0x330
#define B43_MMIO_PIO_BASE4		0x340
#define B43_MMIO_PIO_BASE5		0x350
#define B43_MMIO_PIO_BASE6		0x360
#define B43_MMIO_PIO_BASE7		0x370
/* PIO on core rev >= 11 */
#define B43_MMIO_PIO11_BASE0		0x200
#define B43_MMIO_PIO11_BASE1		0x240
#define B43_MMIO_PIO11_BASE2		0x280
#define B43_MMIO_PIO11_BASE3		0x2C0
#define B43_MMIO_PIO11_BASE4		0x300
#define B43_MMIO_PIO11_BASE5		0x340

#define B43_MMIO_RADIO24_CONTROL	0x3D8	/* core rev >= 24 only */
#define B43_MMIO_RADIO24_DATA		0x3DA	/* core rev >= 24 only */
#define B43_MMIO_PHY_VER		0x3E0
#define B43_MMIO_PHY_RADIO		0x3E2
#define B43_MMIO_PHY0			0x3E6
#define B43_MMIO_ANTENNA		0x3E8
#define B43_MMIO_CHANNEL		0x3F0
#define B43_MMIO_CHANNEL_EXT		0x3F4
#define B43_MMIO_RADIO_CONTROL		0x3F6
#define B43_MMIO_RADIO_DATA_HIGH	0x3F8
#define B43_MMIO_RADIO_DATA_LOW		0x3FA
#define B43_MMIO_PHY_CONTROL		0x3FC
#define B43_MMIO_PHY_DATA		0x3FE
#define B43_MMIO_MACFILTER_CONTROL	0x420
#define B43_MMIO_MACFILTER_DATA		0x422
#define B43_MMIO_RCMTA_COUNT		0x43C
#define B43_MMIO_PSM_PHY_HDR		0x492
#define B43_MMIO_RADIO_HWENABLED_LO	0x49A
#define B43_MMIO_GPIO_CONTROL		0x49C
#define B43_MMIO_GPIO_MASK		0x49E
#define B43_MMIO_TXE0_CTL		0x500
#define B43_MMIO_TXE0_AUX		0x502
#define B43_MMIO_TXE0_TS_LOC		0x504
#define B43_MMIO_TXE0_TIME_OUT		0x506
#define B43_MMIO_TXE0_WM_0		0x508
#define B43_MMIO_TXE0_WM_1		0x50A
#define B43_MMIO_TXE0_PHYCTL		0x50C
#define B43_MMIO_TXE0_STATUS		0x50E
#define B43_MMIO_TXE0_MMPLCP0		0x510
#define B43_MMIO_TXE0_MMPLCP1		0x512
#define B43_MMIO_TXE0_PHYCTL1		0x514
#define B43_MMIO_XMTFIFODEF		0x520
#define B43_MMIO_XMTFIFO_FRAME_CNT	0x522	/* core rev>= 16 only */
#define B43_MMIO_XMTFIFO_BYTE_CNT	0x524	/* core rev>= 16 only */
#define B43_MMIO_XMTFIFO_HEAD		0x526	/* core rev>= 16 only */
#define B43_MMIO_XMTFIFO_RD_PTR		0x528	/* core rev>= 16 only */
#define B43_MMIO_XMTFIFO_WR_PTR		0x52A	/* core rev>= 16 only */
#define B43_MMIO_XMTFIFODEF1		0x52C	/* core rev>= 16 only */
#define B43_MMIO_XMTFIFOCMD		0x540
#define B43_MMIO_XMTFIFOFLUSH		0x542
#define B43_MMIO_XMTFIFOTHRESH		0x544
#define B43_MMIO_XMTFIFORDY		0x546
#define B43_MMIO_XMTFIFOPRIRDY		0x548
#define B43_MMIO_XMTFIFORQPRI		0x54A
#define B43_MMIO_XMTTPLATETXPTR		0x54C
#define B43_MMIO_XMTTPLATEPTR		0x550
#define B43_MMIO_SMPL_CLCT_STRPTR	0x552	/* core rev>= 22 only */
#define B43_MMIO_SMPL_CLCT_STPPTR	0x554	/* core rev>= 22 only */
#define B43_MMIO_SMPL_CLCT_CURPTR	0x556	/* core rev>= 22 only */
#define B43_MMIO_XMTTPLATEDATALO	0x560
#define B43_MMIO_XMTTPLATEDATAHI	0x562
#define B43_MMIO_XMTSEL			0x568
#define B43_MMIO_XMTTXCNT		0x56A
#define B43_MMIO_XMTTXSHMADDR		0x56C
#define B43_MMIO_TSF_CFP_START_LOW	0x604
#define B43_MMIO_TSF_CFP_START_HIGH	0x606
#define B43_MMIO_TSF_CFP_PRETBTT	0x612
#define B43_MMIO_TSF_CLK_FRAC_LOW	0x62E
#define B43_MMIO_TSF_CLK_FRAC_HIGH	0x630
#define B43_MMIO_TSF_0			0x632	/* core rev < 3 only */
#define B43_MMIO_TSF_1			0x634	/* core rev < 3 only */
#define B43_MMIO_TSF_2			0x636	/* core rev < 3 only */
#define B43_MMIO_TSF_3			0x638	/* core rev < 3 only */
#define B43_MMIO_RNG			0x65A
#define B43_MMIO_IFSSLOT		0x684	/* Interframe slot time */
#define B43_MMIO_IFSCTL			0x688	/* Interframe space control */
#define B43_MMIO_IFSSTAT		0x690
#define B43_MMIO_IFSMEDBUSYCTL		0x692
#define B43_MMIO_IFTXDUR		0x694
#define  B43_MMIO_IFSCTL_USE_EDCF	0x0004
#define B43_MMIO_POWERUP_DELAY		0x6A8
#define B43_MMIO_BTCOEX_CTL		0x6B4 /* Bluetooth Coexistence Control */
#define B43_MMIO_BTCOEX_STAT		0x6B6 /* Bluetooth Coexistence Status */
#define B43_MMIO_BTCOEX_TXCTL		0x6B8 /* Bluetooth Coexistence Transmit Control */
#define B43_MMIO_WEPCTL			0x7C0

/* SPROM boardflags_lo values */
#define B43_BFL_BTCOEXIST		0x0001	/* implements Bluetooth coexistance */
#define B43_BFL_PACTRL			0x0002	/* GPIO 9 controlling the PA */
#define B43_BFL_AIRLINEMODE		0x0004	/* implements GPIO 13 radio disable indication */
#define B43_BFL_RSSI			0x0008	/* software calculates nrssi slope. */
#define B43_BFL_ENETSPI			0x0010	/* has ephy roboswitch spi */
#define B43_BFL_XTAL_NOSLOW		0x0020	/* no slow clock available */
#define B43_BFL_CCKHIPWR		0x0040	/* can do high power CCK transmission */
#define B43_BFL_ENETADM			0x0080	/* has ADMtek switch */
#define B43_BFL_ENETVLAN		0x0100	/* can do vlan */
#define B43_BFL_AFTERBURNER		0x0200	/* supports Afterburner mode */
#define B43_BFL_NOPCI			0x0400	/* leaves PCI floating */
#define B43_BFL_FEM			0x0800	/* supports the Front End Module */
#define B43_BFL_EXTLNA			0x1000	/* has an external LNA */
#define B43_BFL_HGPA			0x2000	/* had high gain PA */
#define B43_BFL_BTCMOD			0x4000	/* BFL_BTCOEXIST is given in alternate GPIOs */
#define B43_BFL_ALTIQ			0x8000	/* alternate I/Q settings */

/* SPROM boardflags_hi values */
#define B43_BFH_NOPA			0x0001	/* has no PA */
#define B43_BFH_RSSIINV			0x0002	/* RSSI uses positive slope (not TSSI) */
#define B43_BFH_PAREF			0x0004	/* uses the PARef LDO */
#define B43_BFH_3TSWITCH		0x0008	/* uses a triple throw switch shared
						 * with bluetooth */
#define B43_BFH_PHASESHIFT		0x0010	/* can support phase shifter */
#define B43_BFH_BUCKBOOST		0x0020	/* has buck/booster */
#define B43_BFH_FEM_BT			0x0040	/* has FEM and switch to share antenna
						 * with bluetooth */
#define B43_BFH_NOCBUCK			0x0080
#define B43_BFH_PALDO			0x0200
#define B43_BFH_EXTLNA_5GHZ		0x1000	/* has an external LNA (5GHz mode) */

/* SPROM boardflags2_lo values */
#define B43_BFL2_RXBB_INT_REG_DIS	0x0001	/* external RX BB regulator present */
#define B43_BFL2_APLL_WAR		0x0002	/* alternative A-band PLL settings implemented */
#define B43_BFL2_TXPWRCTRL_EN 		0x0004	/* permits enabling TX Power Control */
#define B43_BFL2_2X4_DIV		0x0008	/* 2x4 diversity switch */
#define B43_BFL2_5G_PWRGAIN		0x0010	/* supports 5G band power gain */
#define B43_BFL2_PCIEWAR_OVR		0x0020	/* overrides ASPM and Clkreq settings */
#define B43_BFL2_CAESERS_BRD		0x0040	/* is Caesers board (unused) */
#define B43_BFL2_BTC3WIRE		0x0080	/* used 3-wire bluetooth coexist */
#define B43_BFL2_SKWRKFEM_BRD		0x0100	/* 4321mcm93 uses Skyworks FEM */
#define B43_BFL2_SPUR_WAR		0x0200	/* has a workaround for clock-harmonic spurs */
#define B43_BFL2_GPLL_WAR		0x0400	/* altenative G-band PLL settings implemented */
#define B43_BFL2_SINGLEANT_CCK		0x1000
#define B43_BFL2_2G_SPUR_WAR		0x2000

/* SPROM boardflags2_hi values */
#define B43_BFH2_GPLL_WAR2		0x0001
#define B43_BFH2_IPALVLSHIFT_3P3	0x0002
#define B43_BFH2_INTERNDET_TXIQCAL	0x0004
#define B43_BFH2_XTALBUFOUTEN		0x0008

/* GPIO register offset, in both ChipCommon and PCI core. */
#define B43_GPIO_CONTROL		0x6c

/* SHM Routing */
enum {
	B43_SHM_UCODE,		/* Microcode memory */
	B43_SHM_SHARED,		/* Shared memory */
	B43_SHM_SCRATCH,	/* Scratch memory */
	B43_SHM_HW,		/* Internal hardware register */
	B43_SHM_RCMTA,		/* Receive match transmitter address (rev >= 5 only) */
};
/* SHM Routing modifiers */
#define B43_SHM_AUTOINC_R		0x0200	/* Auto-increment address on read */
#define B43_SHM_AUTOINC_W		0x0100	/* Auto-increment address on write */
#define B43_SHM_AUTOINC_RW		(B43_SHM_AUTOINC_R | \
					 B43_SHM_AUTOINC_W)

/* Misc SHM_SHARED offsets */
#define B43_SHM_SH_WLCOREREV		0x0016	/* 802.11 core revision */
#define B43_SHM_SH_PCTLWDPOS		0x0008
#define B43_SHM_SH_RXPADOFF		0x0034	/* RX Padding data offset (PIO only) */
#define B43_SHM_SH_FWCAPA		0x0042	/* Firmware capabilities (Opensource firmware only) */
#define B43_SHM_SH_PHYVER		0x0050	/* PHY version */
#define B43_SHM_SH_PHYTYPE		0x0052	/* PHY type */
#define B43_SHM_SH_ANTSWAP		0x005C	/* Antenna swap threshold */
#define B43_SHM_SH_HOSTF1		0x005E	/* Hostflags 1 for ucode options */
#define B43_SHM_SH_HOSTF2		0x0060	/* Hostflags 2 for ucode options */
#define B43_SHM_SH_HOSTF3		0x0062	/* Hostflags 3 for ucode options */
#define B43_SHM_SH_RFATT		0x0064	/*