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/*********************************************************************
*
* Filename: via-ircc.h
* Version: 1.0
* Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
* Author: VIA Technologies, inc
* Date : 08/06/2003
Copyright (c) 1998-2003 VIA Technologies, Inc.
This program is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free Software
Foundation; either version 2, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with
this program; if not, see <http://www.gnu.org/licenses/>.
* Comment:
* jul/08/2002 : Rx buffer length should use Rx ring ptr.
* Oct/28/2002 : Add SB id for 3147 and 3177.
* jul/09/2002 : only implement two kind of dongle currently.
* Oct/02/2002 : work on VT8231 and VT8233 .
* Aug/06/2003 : change driver format to pci driver .
********************************************************************/
#ifndef via_IRCC_H
#define via_IRCC_H
#include <linux/time.h>
#include <linux/spinlock.h>
#include <linux/pm.h>
#include <linux/types.h>
#include <asm/io.h>
#define MAX_TX_WINDOW 7
#define MAX_RX_WINDOW 7
struct st_fifo_entry {
int status;
int len;
};
struct st_fifo {
struct st_fifo_entry entries[MAX_RX_WINDOW + 2];
int pending_bytes;
int head;
int tail;
int len;
};
struct frame_cb {
void *start; /* Start of frame in DMA mem */
int len; /* Length of frame in DMA mem */
};
struct tx_fifo {
struct frame_cb queue[MAX_TX_WINDOW + 2]; /* Info about frames in queue */
int ptr; /* Currently being sent */
int len; /* Length of queue */
int free; /* Next free slot */
void *tail; /* Next free start in DMA mem */
};
struct eventflag // for keeping track of Interrupt Events
{
//--------tx part
unsigned char TxFIFOUnderRun;
unsigned char EOMessage;
unsigned char TxFIFOReady;
unsigned char EarlyEOM;
//--------rx part
unsigned char PHYErr;
unsigned char CRCErr;
unsigned char RxFIFOOverRun;
unsigned char EOPacket;
unsigned char RxAvail;
unsigned char TooLargePacket;
unsigned char SIRBad;
//--------unknown
unsigned char Unknown;
//----------
unsigned char TimeOut;
unsigned char RxDMATC;
unsigned char TxDMATC;
};
/* Private data for each instance */
struct via_ircc_cb {
struct st_fifo st_fifo; /* Info about received frames */
struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
struct net_device *netdev; /* Yes! we are some kind of netdevice */
struct irlap_cb *irlap; /* The link layer we are binded to */
struct qos_info qos; /* QoS capabilities for this device */
chipio_t io; /* IrDA controller information */
iobuff_t tx_buff; /* Transmit buffer */
iobuff_t rx_buff; /* Receive buffer */
dma_addr_t tx_buff_dma;
dma_addr_t rx_buff_dma;
__u8 ier; /* Interrupt enable register */
struct timeval stamp;
struct timeval now;
spinlock_t lock; /* For serializing operations */
__u32 flags; /* Interface flags */
__u32 new_speed;
int index; /* Instance index */
struct eventflag EventFlag;
unsigned int chip_id; /* to remember chip id */
unsigned int RetryCount;
unsigned int RxDataReady;
unsigned int RxLastCount;
};
//---------I=Infrared, H=Host, M=Misc, T=Tx, R=Rx, ST=Status,
// CF=Config, CT=Control, L=Low, H=High, C=Count
#define I_CF_L_0 0x10
#define I_CF_H_0 0x11
#define I_SIR_BOF 0x12
#define I_SIR_EOF 0x13
#define I_ST_CT_0 0x15
#define I_ST_L_1 0x16
#define I_ST_H_1 0x17
#define I_CF_L_1 0x18
#define I_CF_H_1 0x19
#define I_CF_L_2 0x1a
#define I_CF_H_2 0x1b
#define I_CF_3 0x1e
#define H_CT 0x20
#define H_ST 0x21
#define M_CT 0x22
#define TX_CT_1 0x23
#define TX_CT_2 0x24
#define TX_ST 0x25
#define RX_CT 0x26
#define RX_ST 0x27
#define RESET 0x28
#define P_ADDR 0x29
#define RX_C_L 0x2a
#define RX_C_H 0x2b
#define RX_P_L 0x2c
#define RX_P_H 0x2d
#define TX_C_L 0x2e
#define TX_C_H 0x2f
#define TIMER 0x32
#define I_CF_4 0x33
#define I_T_C_L 0x34
#define I_T_C_H 0x35
#define VERSION 0x3f
//-------------------------------
#define StartAddr 0x10 // the first register address
#define EndAddr 0x3f // the last register address
#define GetBit(val,bit) val = (unsigned char) ((val>>bit) & 0x1)
// Returns the bit
#define SetBit(val,bit) val= (unsigned char ) (val | (0x1 << bit))
// Sets bit to 1
#define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit))
// Sets bit to 0
#define OFF 0
#define ON 1
#define DMA_TX_MODE 0x08
#define DMA_RX_MODE 0x04
#define DMA1 0
#define DMA2 0xc0
#define MASK1 DMA1+0x0a
#define MASK2 DMA2+0x14
#define Clk_bit 0x40
#define Tx_bit 0x01
#define Rd_Valid 0x08
#define RxBit 0x08
static void DisableDmaChannel(unsigned int channel)
{
switch (channel) { // 8 Bit DMA channels DMAC1
case 0:
outb(4, MASK1); //mask channel 0
break;
case 1:
outb(5, MASK1); //Mask channel 1
break;
case 2:
outb(6, MASK1); //Mask channel 2
break;
case 3:
outb(7, MASK1); //Mask channel 3
break;
case 5:
outb(5, MASK2); //Mask channel 5
break;
case 6:
outb(6, MASK2); //Mask channel 6
break;
case 7:
outb(7, MASK2); //Mask channel 7
break;
default:
break;
}
}
static unsigned char ReadLPCReg(int iRegNum)
{
unsigned char iVal;
outb(0x87, 0x2e);
outb(0x87, 0x2e);
outb(iRegNum, 0x2e);
iVal = inb(0x2f);
outb(0xaa, 0x2e);
return iVal;
}
static void WriteLPCReg(int iRegNum, unsigned char iVal)
{
outb(0x87, 0x2e);
outb(0x87, 0x2e);
outb(iRegNum, 0x2e);
outb(iVal, 0x2f);
outb(0xAA, 0x2e);
}
static __u8 ReadReg(unsigned int BaseAddr, int iRegNum)
{
return (__u8) inb(BaseAddr + iRegNum);
}
static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)
{
outb(iVal, BaseAddr + iRegNum);
}
static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,
unsigned char BitPos, unsigned char value)
{
__u8 Rtemp, Wtemp;
if (BitPos > 7) {
return
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