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|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
* stmmac XGMAC support.
*/
#include <linux/bitrev.h>
#include <linux/crc32.h>
#include "stmmac.h"
#include "dwxgmac2.h"
static void dwxgmac2_core_init(struct mac_device_info *hw,
struct net_device *dev)
{
void __iomem *ioaddr = hw->pcsr;
int mtu = dev->mtu;
u32 tx, rx;
tx = readl(ioaddr + XGMAC_TX_CONFIG);
rx = readl(ioaddr + XGMAC_RX_CONFIG);
tx |= XGMAC_CORE_INIT_TX;
rx |= XGMAC_CORE_INIT_RX;
if (mtu >= 9000) {
rx |= XGMAC_CONFIG_GPSLCE;
rx |= XGMAC_JUMBO_LEN << XGMAC_CONFIG_GPSL_SHIFT;
rx |= XGMAC_CONFIG_WD;
} else if (mtu > 2000) {
rx |= XGMAC_CONFIG_JE;
} else if (mtu > 1500) {
rx |= XGMAC_CONFIG_S2KP;
}
if (hw->ps) {
tx |= XGMAC_CONFIG_TE;
tx &= ~hw->link.speed_mask;
switch (hw->ps) {
case SPEED_10000:
tx |= hw->link.xgmii.speed10000;
break;
case SPEED_2500:
tx |= hw->link.speed2500;
break;
case SPEED_1000:
default:
tx |= hw->link.speed1000;
break;
}
}
writel(tx, ioaddr + XGMAC_TX_CONFIG);
writel(rx, ioaddr + XGMAC_RX_CONFIG);
writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN);
}
static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)
{
u32 tx = readl(ioaddr + XGMAC_TX_CONFIG);
u32 rx = readl(ioaddr + XGMAC_RX_CONFIG);
if (enable) {
tx |= XGMAC_CONFIG_TE;
rx |= XGMAC_CONFIG_RE;
} else {
tx &= ~XGMAC_CONFIG_TE;
rx &= ~XGMAC_CONFIG_RE;
}
writel(tx, ioaddr + XGMAC_TX_CONFIG);
writel(rx, ioaddr + XGMAC_RX_CONFIG);
}
static int dwxgmac2_rx_ipc(struct mac_device_info *hw)
{
void __iomem *ioaddr = hw->pcsr;
u32 value;
value = readl(ioaddr + XGMAC_RX_CONFIG);
if (hw->rx_csum)
value |= XGMAC_CONFIG_IPC;
else
value &= ~XGMAC_CONFIG_IPC;
writel(value, ioaddr + XGMAC_RX_CONFIG);
return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC);
}
static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
u32 queue)
{
void __iomem *ioaddr = hw->pcsr;
u32 value;
value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue);
if (mode == MTL_QUEUE_AVB)
value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
else if (mode == MTL_QUEUE_DCB)
value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
writel(value, ioaddr + XGMAC_RXQ_CTRL0);
}
static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,
u32 queue)
{
void __iomem *ioaddr = hw->pcsr;
u32 value, reg;
reg = (queue < 4) ? XGMAC_RXQ_CTRL2 : XGMAC_RXQ_CTRL3;
value = readl(ioaddr + reg);
value &= ~XGMAC_PSRQ(queue);
value |= (prio << XGMAC_PSRQ_SHIFT(queue)) & XGMAC_PSRQ(queue);
writel(value, ioaddr + reg);
}
static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
u32 rx_alg)
{
void __iomem *ioaddr = hw->pcsr;
u32 value;
value = readl(ioaddr + XGMAC_MTL_OPMODE);
value &= ~XGMAC_RAA;
switch (rx_alg) {
case MTL_RX_ALGORITHM_SP:
break;
case MTL_RX_ALGORITHM_WSP:
value |= XGMAC_RAA;
break;
default:
break;
}
writel(value, ioaddr + XGMAC_MTL_OPMODE);
}
static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,
u32 tx_alg)
{
void __iomem *ioaddr = hw->pcsr;
u32 value;
value = readl(ioaddr + XGMAC_MTL_OPMODE);
value &= ~XGMAC_ETSALG;
switch (tx_alg) {
case MTL_TX_ALGORITHM_WRR:
value |= XGMAC_WRR;
break;
case MTL_TX_ALGORITHM_WFQ:
value |= XGMAC_WFQ;
break;
case MTL_TX_ALGORITHM_DWRR:
value |= XGMAC_DWRR;
break;
default:
break;
}
writel(value, ioaddr + XGMAC_MTL_OPMODE);
}
static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,
u32 chan)
{
void __iomem *ioaddr = hw->pcsr;
u32 value, reg;
reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1;
value = readl(ioaddr + reg);
value &= ~XGMAC_QxMDMACH(queue);
value |= (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue);
writel(value, ioaddr + reg);
}
static void dwxgmac2_config_cbs(struct mac_device_info *hw,
u32 send_slope, u32 idle_slope,
u32 high_credit, u32 low_credit, u32 queue)
{
void __iomem *ioaddr = hw->pcsr;
u32 value;
writel(send_slope, ioaddr + XGMAC_MTL_TCx_SENDSLOPE(queue));
writel(idle_slope, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
writel(high_credit, ioaddr + XGMAC_MTL_TCx_HICREDIT(queue));
writel(low_credit, ioaddr + XGMAC_MTL_TCx_LOCREDIT(queue));
value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
value |= XGMAC_CC | XGMAC_CBS;
writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
}
static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
struct stmmac_extra_stats *x)
{
void __iomem *ioaddr = hw->pcsr;
u32 stat, en;
en = readl(ioaddr + XGMAC_INT_EN);
stat = readl(ioaddr + XGMAC_INT_STATUS);
stat &= en;
if (stat & XGMAC_PMTIS) {
x->irq_receive_pmt_irq_n++;
readl(ioaddr + XGMAC_PMT);
}
return 0;
}
static int dwxgmac2_host_mtl_irq_status(struct mac_device_info *hw, u32 chan)
{
void __iomem *ioaddr = hw->pcsr;
int ret = 0;
u32 status;
status = readl(ioaddr + XGMAC_MTL_INT_STATUS);
if (status & BIT(chan)) {
u32 chan_status = readl(
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