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/*
* QLogic qlcnic NIC Driver
* Copyright (c) 2009-2013 QLogic Corporation
*
* See LICENSE.qlcnic for copyright and licensing details.
*/
#ifndef __QLCNIC_83XX_HW_H
#define __QLCNIC_83XX_HW_H
#include <linux/types.h>
#include <linux/etherdevice.h>
#include "qlcnic_hw.h"
#define QLCNIC_83XX_BAR0_LENGTH 0x4000
/* Directly mapped registers */
#define QLC_83XX_CRB_WIN_BASE 0x3800
#define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4))
#define QLC_83XX_SEM_LOCK_BASE 0x3840
#define QLC_83XX_SEM_UNLOCK_BASE 0x3844
#define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8))
#define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
#define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
#define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
#define QLC_83XX_LINK_SPEED_FACTOR 10
#define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
#define QLC_83XX_INTX_PTR 0x38C0
#define QLC_83XX_INTX_TRGR 0x38C4
#define QLC_83XX_INTX_MASK 0x38C8
#define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100
#define QLC_83XX_DRV_LOCK_WAIT_DELAY 20
#define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1
#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2
#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3
#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200
#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3
#define QLC_83XX_LB_WAIT_COUNT 250
#define QLC_83XX_LB_MSLEEP_COUNT 20
#define QLC_83XX_NO_NIC_RESOURCE 0x5
#define QLC_83XX_MAC_PRESENT 0xC
#define QLC_83XX_MAC_ABSENT 0xD
#define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024)
/* PEG status definitions */
#define QLC_83XX_CMDPEG_COMPLETE 0xff01
#define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30)
#define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31)
#define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF)
#define QLC_83XX_LEGACY_INTX_MAX_RETRY 100
#define QLC_83XX_LEGACY_INTX_DELAY 4
#define QLC_83XX_REG_DESC 1
#define QLC_83XX_LRO_DESC 2
#define QLC_83XX_CTRL_DESC 3
#define QLC_83XX_FW_CAPABILITY_TSO BIT_6
#define QLC_83XX_FW_CAP_LRO_MSS BIT_17
#define QLC_83XX_HOST_RDS_MODE_UNIQUE 0
#define QLC_83XX_HOST_SDS_MBX_IDX 8
#define QLCNIC_HOST_RDS_MBX_IDX 88
/* Pause control registers */
#define QLC_83XX_SRE_SHIM_REG 0x0D200284
#define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4
#define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4
#define QLC_83XX_PORT0_TC_MC_REG 0x0B200388
#define QLC_83XX_PORT1_TC_MC_REG 0x0B201388
#define QLC_83XX_PORT0_TC_STATS 0x0B20039C
#define QLC_83XX_PORT1_TC_STATS 0x0B20139C
#define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704
#define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704
/* Peg PC status registers */
#define QLC_83XX_CRB_PEG_NET_0 0x3400003c
#define QLC_83XX_CRB_PEG_NET_1 0x3410003c
#define QLC_83XX_CRB_PEG_NET_2 0x3420003c
#define QLC_83XX_CRB_PEG_NET_3 0x3430003c
#define QLC_83XX_CRB_PEG_NET_4 0x34b0003c
/* Firmware image definitions */
#define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000
#define QLC_83XX_FW_FILE_NAME "83xx_fw.bin"
#define QLC_84XX_FW_FILE_NAME "84xx_fw.bin"
#define QLC_83XX_BOOT_FROM_FLASH 0
#define QLC_83XX_BOOT_FROM_FILE 0x12345678
#define QLC_FW_FILE_NAME_LEN 20
#define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16
#define QLC_83XX_MBX_POST_BC_OP 0x1
#define QLC_83XX_MBX_COMPLETION 0x0
#define QLC_83XX_MBX_REQUEST 0x1
#define QLC_83XX_MBX_TIMEOUT (5 * HZ)
#define QLC_83XX_MBX_CMD_LOOP 5000000
/* status descriptor mailbox data
* @phy_addr_{low|high}: physical address of buffer
* @sds_ring_size: buffer size
* @intrpt_id: interrupt id
* @intrpt_val: source of interrupt
*/
struct qlcnic_sds_mbx {
u32 phy_addr_low;
u32 phy_addr_high;
u32 rsvd1[4];
#if defined(__LITTLE_ENDIAN)
u16 sds_ring_size;
u16 rsvd2;
u16 rsvd3[2];
u16 intrpt_id;
u8 intrpt_val;
u8 rsvd4;
#elif defined(__BIG_ENDIAN)
u16 rsvd2;
u16 sds_ring_size;
u16 rsvd3[2];
u8 rsvd4;
u8 intrpt_val;
u16 intrpt_id;
#endif
u32 rsvd5;
} __packed;
/* receive descriptor buffer data
* phy_addr_reg_{low|high}: physical address of regular buffer
* phy_addr_jmb_{low|high}: physical address of jumbo buffer
* reg_ring_sz: size of regular buffer
* reg_ring_len: no. of entries in regular buffer
* jmb_ring_len: no. of entries in jumbo buffer
* jmb_ring_sz: size of jumbo buffer
*/
struct qlcnic_rds_mbx {
u32 phy_addr_reg_low;
u32 phy_addr_reg_high;
u32 phy_addr_jmb_low;
u32 phy_addr_jmb_high;
#if defined(__LITTLE_ENDIAN)
u16 reg_ring_sz;
u16 reg_ring_len;
u16 jmb_ring_sz;
u16 jmb_ring_len;
#elif defined(__BIG_ENDIAN)
u16 reg_ring_len;
u16 reg_ring_sz;
u16 jmb_ring_len;
u16 jmb_ring_sz;
#endif
} __packed;
/* host producers for regular and jumbo rings */
struct __host_producer_mbx {
u32 reg_buf;
u32 jmb_buf;
} __packed;
/* Receive context mailbox data outbox registers
* @state: state of the context
* @vport_id: virtual port id
* @context_id: receive context id
* @num_pci_func: number of pci functions of the port
* @phy_port: physical port id
*/
struct qlcnic_rcv_mbx_out {
#if defined(__LITTLE_ENDIAN)
u8 rcv_num;
u8 sts_num;
u16 ctx_id;
u8 state;
u8 num_pci_func;
u8 phy_port;
u8 vport_id;
#elif defined(__BIG_ENDIAN)
u16 ctx_id;
u8 sts_num;
u8 rcv_num;
u8 vport_id;
u8 phy_port;
u8 num_pci_func;
u8 state;
#endif
u32 host_csmr[QLCNIC_MAX_SDS_RINGS];
struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS];
} __packed;
struct qlcnic_add_rings_mbx_out {
#if defined(__LITTLE_ENDIAN)
u8 rcv_num;
u8 sts_num;
u16 ctx_id;
#elif defined(__BIG_ENDIAN)
u16 ctx_id;
u8 sts_num;
u8 rcv_num;
#endif
u32 host_csmr[QLCNIC_MAX_SDS_RINGS];
struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS];
} __packed;
/* Transmit context mailbox inbox registers
* @phys_addr_{low|high}: DMA address of the transmit buffer
* @cnsmr_index_{low|high}: host consumer index
* @size: legth of transmit buffer ring
* @intr_id: interrput id
* @src: src of interrupt
*/
struct qlcnic_tx_mbx {
u32 phys_addr_low;
u32 phys_addr_high;
u32 cnsmr_index_low;
u32 cnsmr_index_high;
#if defined(__LITTLE_ENDIAN)
u16 size;
u16 intr_id;
u8 src;
u8 rsvd[3];
#elif defined(__BIG_ENDIAN)
u16 intr_id;
u16 size;
u8 rsvd[3];
u8 src;
#endif
} __packed;
/* Transmit context mailbox outbox registers
* @host_prod: host producer index
* @ctx_id: transmit context id
* @state: state of the transmit context
*/
struct qlcnic_tx_mbx_out {
u32 host_prod;
#if defined(__LITTLE_ENDIAN)
u16 ctx_id;
u8 state;
u8 rsvd;
#elif defined(__BIG_ENDIAN)
u8 rsvd;
u8 state;
u16 ctx_id;
#endif
} __packed;
struct qlcnic_intrpt_config {
u8 type;
u8 enabled;
u16 id;
u32 src;
};
struct qlcnic_macvlan_mbx {
#if defined(__LITTLE_ENDIAN)
u8 mac_addr0;
u8 mac_addr1;
u8 mac_addr2;
u8 mac_addr3;
u8 mac_addr4;
u8 mac_addr5;
u16 vlan;
#elif defined(__BIG_ENDIAN)
u8 mac_addr3;
u8 mac_addr2;
u8 mac_addr1;
u8 mac_addr0;
u16 vlan;
u8 mac_addr5;
u8 mac_addr4;
#endif
};
struct qlc_83xx_fw_info {
const struct firmware *fw;
char fw_file_name[QLC_FW_FILE_NAME_LEN];
};
struct qlc_83xx_reset {
struct qlc_83xx_reset_hdr *hdr;
int seq_index;
int seq_error;
int array_index;
u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
u8 *buff;
u8 *stop_offset;
u8 *start_offset;
u8 *init_offset;
u8 seq_end;
u8 template_end;
};
#define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1
#define QLC_83XX_IDC_GRACEFULL_RESET 0x2
#define QLC_83XX_IDC_DISABLE_FW_DUMP 0x4
#define QLC_83XX_IDC_TIMESTAMP 0
#define QLC_83XX_IDC_DURATION 1
#define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30
#define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10
#define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10
#define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20
#define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ)
#define QLC_83XX_IDC_FW_FAIL_THRESH 2
#define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8
#define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16
#define QLC_83XX_IDC_MAJOR_VERSION 1
#define QLC_83XX_IDC_MINOR_VERSION 0
#define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020
struct qlcnic_adapter;
struct qlc_83xx_idc {
int (*state_entry) (struct qlcnic_adapter *);
u64 sec_counter;
u64 delay;
unsigned long status;
int err_code;
int collect_dump;
u8 curr_state;
u8 prev_state;
u8 vnic_state;
u8 vnic_wait_limit;
u8 quiesce_req;
u8 delay_reset;
char **name;
};
/* Device States */
enum qlcnic_83xx_states {
QLC_83XX_IDC_DEV_UNKNOWN,
QLC_83XX_IDC_DEV_COLD,
QLC_83XX_IDC_DEV_INIT,
QLC_83XX_IDC_DEV_READY,
QLC_83XX_IDC_DEV_NEED_RESET,
QLC_83XX_IDC_DEV_NEED_QUISCENT,
QLC_83XX_IDC_DEV_FAILED,
QLC_83XX_IDC_DEV_QUISCENT
};
#define QLCNIC_MBX_RSP(reg) LSW(reg)
#define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF)
#define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F)
#define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4))
#define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4))
/* Mailbox process AEN count */
#define QLC_83XX_IDC_COMP_AEN 3
#define QLC_83XX_MBX_AEN_CNT 5
#define QLC_83XX_MODULE_LOADED 1
#define QLC_83XX_MBX_READY 2
#define QLC_83XX_MBX_AEN_ACK 3
#define QLC_83XX_SFP_PRESENT(data) ((data) & 3)
#define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3)
#define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F)
#define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16))
#define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10)
#define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11)
#define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
#define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7)
#define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3)
#define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7)
#define QLC_83XX_LINK_FEC(data) ((data) & BIT_12)
#define QLC_83XX_LINK_EEE(data) ((data) & BIT_13)
#define QLC_83XX_DCBX(data) (((data) >> 28) & 7)
#define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
#define QLC_83XX_TX_PAUSE 0x10
#define QLC_83XX_RX_PAUSE 0x20
#define QLC_83XX_TX_RX_PAUSE 0x30
#define QLC_83XX_CFG_STD_PAUSE (1 << 5)
#define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20)
#define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20)
#define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20)
#define QLC_83XX_ENABLE_AUTONEG (1 << 15)
#define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1)
#define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1)
#define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1)
/* LED configuration settings */
#define QLC_83XX_ENABLE_BEACON 0xe
#define QLC_83XX_LED_RATE 0xff
#define QLC_83XX_LED_ACT (1 << 10)
#define QLC_83XX_LED_MOD (0 << 13)
#define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
QLC_83XX_LED_MOD)
#define QLC_83XX_10M_LINK 1
#define QLC_83XX_100M_LINK 2
#define QLC_83XX_1G_LINK 3
#define QLC_83XX_10G_LINK 4
#define QLC_83XX_STAT_TX 3
#define QLC_83XX_STAT_RX 2
#define QLC_83XX_STAT_MAC 1
#define QLC_83XX_TX_STAT_REGS 14
#define QLC_83XX_RX_STAT_REGS 40
#define QLC_83XX_MAC_STAT_REGS 94
#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
#define QLC_83XX
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