blob: 0e82b6368798a2cf02cfef922b4feffa2ff779d1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
|
/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (C) 2018 Microchip Technology Inc. */
#ifndef _LAN743X_H
#define _LAN743X_H
#include "lan743x_ptp.h"
#define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
#define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
#define DRIVER_NAME "lan743x"
/* Register Definitions */
#define ID_REV (0x00)
#define ID_REV_ID_MASK_ (0xFFFF0000)
#define ID_REV_ID_LAN7430_ (0x74300000)
#define ID_REV_ID_LAN7431_ (0x74310000)
#define ID_REV_IS_VALID_CHIP_ID_(id_rev) \
(((id_rev) & 0xFFF00000) == 0x74300000)
#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
#define ID_REV_CHIP_REV_A0_ (0x00000000)
#define ID_REV_CHIP_REV_B0_ (0x00000010)
#define FPGA_REV (0x04)
#define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
#define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
#define HW_CFG (0x010)
#define HW_CFG_LRST_ BIT(1)
#define PMT_CTL (0x014)
#define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27)
#define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25)
#define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24)
#define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23)
#define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18)
#define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15)
#define PMT_CTL_EEE_WAKEUP_EN_ BIT(13)
#define PMT_CTL_READY_ BIT(7)
#define PMT_CTL_ETH_PHY_RST_ BIT(4)
#define PMT_CTL_WOL_EN_ BIT(3)
#define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)
#define PMT_CTL_WUPS_MASK_ (0x00000003)
#define DP_SEL (0x024)
#define DP_SEL_DPRDY_ BIT(31)
#define DP_SEL_MASK_ (0x0000001F)
#define DP_SEL_RFE_RAM (0x00000001)
#define DP_SEL_VHF_HASH_LEN (16)
#define DP_SEL_VHF_VLAN_LEN (128)
#define DP_CMD (0x028)
#define DP_CMD_WRITE_ (0x00000001)
#define DP_ADDR (0x02C)
#define DP_DATA_0 (0x030)
#define E2P_CMD (0x040)
#define E2P_CMD_EPC_BUSY_ BIT(31)
#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
#define E2P_CMD_EPC_TIMEOUT_ BIT(10)
#define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
#define E2P_DATA (0x044)
#define GPIO_CFG0 (0x050)
#define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit))
#define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
#define GPIO_CFG1 (0x054)
#define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit))
#define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
#define GPIO_CFG2 (0x058)
#define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
#define GPIO_CFG3 (0x05C)
#define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit))
#define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
#define FCT_RX_CTL (0xAC)
#define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))
#define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))
#define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel))
#define FCT_TX_CTL (0xC4)
#define FCT_TX_CTL_EN_(channel) BIT(28 + (channel))
#define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel))
#define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel))
#define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
#define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
#define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \
((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
#define FCT_FLOW_CTL_REQ_EN_ BIT(7)
#define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
#define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \
((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
#define MAC_CR (0x100)
#define MAC_CR_EEE_EN_ BIT(17)
#define MAC_CR_ADD_ BIT(12)
#define MAC_CR_ASD_ BIT(11)
#define MAC_CR_CNTR_RST_ BIT(5)
#define MAC_CR_RST_ BIT(0)
#define MAC_RX (0x104)
#define MAC_RX_MAX_SIZE_SHIFT_ (16)
#define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
#define MAC_RX_RXD_ BIT(1)
#define MAC_RX_RXEN_ BIT(0)
#define MAC_TX (0x108)
#define MAC_TX_TXD_ BIT(1)
#define MAC_TX_TXEN_ BIT(0)
#define MAC_FLOW (0x10C)
#define MAC_FLOW_CR_TX_FCEN_ BIT(30)
#define MAC_FLOW_CR_RX_FCEN_ BIT(29)
#define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
#define MAC_RX_ADDRH (0x118)
#define MAC_RX_ADDRL (0x11C)
#define MAC_MII_ACC (0x120)
#define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)
#define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
#define MAC_MII_ACC_MIIRINDA_SHIFT_ (6)
#define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
#define MAC_MII_ACC_MII_READ_ (0x00000000)
#define MAC_MII_ACC_MII_WRITE_ (0x00000002)
#define MAC_MII_ACC_MII_BUSY_ BIT(0)
#define MAC_MII_DATA (0x124)
#define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
#define MAC_WUCSR (0x140)
#define MAC_WUCSR_RFE_WAKE_EN_ BIT(14)
#define MAC_WUCSR_PFDA_EN_ BIT(3)
#define MAC_WUCSR_WAKE_EN_ BIT(2)
#define MAC_WUCSR_MPEN_ BIT(1)
#define MAC_WUCSR_BCST_EN_ BIT(0)
#define MAC_WK_SRC (0x144)
#define MAC_WUF_CFG0 (0x150)
#define MAC_NUM_OF_WUF_CFG (32)
#define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0)
#define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index)))
#define MAC_WUF_CFG_EN_ BIT(31)
#define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)
#define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)
#define MAC_WUF_CFG_OFFSET_SHIFT_ (16)
#define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)
#define MAC_WUF_MASK0_0 (0x200)
#define MAC_WUF_MASK0_1 (0x204)
#define MAC_WUF_MASK0_2 (0x208)
#define MAC_WUF_MASK0_3 (0x20C)
#define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0)
#define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1)
#define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2)
#define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3)
#define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
#define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
#define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
#define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
/* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
#define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
#define RFE_ADDR_FILT_HI_VALID_ BIT(31)
/* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
#define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
#define RFE_CTL (0x508)
#define RFE_CTL_AB_ BIT(10)
#define RFE_CTL_AM_ BIT(9)
#define RFE_CTL_AU_ BIT(8)
#define RFE_CTL_MCAST_HASH_ BIT(3)
#define RFE_CTL_DA_PERFECT_ BIT(1)
#define RFE_RSS_CFG (0x554)
#define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16)
#define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15)
#define RFE_RSS_CFG_IPV6_EX_ BIT(14)
#define RFE_RSS_CFG_UDP_IPV6_ BIT(13)
#define RFE_RSS_CFG_TCP_IPV6_ BIT(12)
#define RFE_RSS_CFG_IPV6_ BIT(11)
#define RFE_RSS_CFG_UDP_IPV4_ BIT(10)
#define RFE_RSS_CFG_TCP_IPV4_ BIT(9)
#define RFE_RSS_CFG_IPV4_ BIT(8)
#define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)
#define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2)
#define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1)
#define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)
#define RFE_HASH_KEY(index) (0x558 + (index << 2))
#define RFE_INDX(index) (0x580 + (index << 2))
#define MAC_WUCSR2 (0x600)
#define INT_STS (0x780)
#define INT_BIT_DMA_RX_(channel) BIT(24 + (channel))
#define INT_BIT_ALL_RX_ (0x0F000000)
#define INT_BIT_DMA_TX_(channel) BIT(16 + (channel))
#define INT_BIT_ALL_TX_ (0x000F0000)
#define INT_BIT_SW_GP_ BIT(9)
#define INT_BIT_1588_ BIT(7)
#define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_)
#define INT_BIT_MAS_ BIT(0)
#define INT_SET (0x784)
#define INT_EN_SET (0x788)
#define INT_EN_CLR (0x78C)
#define INT_STS_R2C (0x790)
#define INT_VEC_EN_SET (0x794)
#define INT_VEC_EN_CLR (0x798)
#define INT_VEC_EN_AUTO_CLR (0x79C)
#define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
#define INT_VEC_MAP0 (0x7A0)
#define INT_VEC_MAP0_RX_VEC_(channel, vector) \
(((u32)(vector)) << ((channel) << 2))
#define INT_VEC_MAP1 (0x7A4)
#define INT_VEC_MAP1_TX_VEC_(channel, vector) \
(((u32)(vector)) << ((channel) << 2))
#define INT_VEC_MAP2 (0x7A8)
#define INT_MOD_MAP0 (0x7B0)
#define INT_MOD_MAP1 (0x7B4)
#define INT_MOD_MAP2 (0x7B8)
#define INT_MOD_CFG0 (0x7C0)
#define INT_MOD_CFG1 (0x7C4)
#define INT_MOD_CFG2 (0x7C8)
#define INT_MOD_CFG3 (0x7CC)
#define INT_MOD_CFG4 (0x7D0)
#define INT_MOD_CFG5 (0x7D4)
#define INT_MOD_CFG6 (0x7D8)
#define INT_MOD_CFG7 (0x7DC)
#define PTP_CMD_CTL (0x0A00)
#define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6)
#define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5)
#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
#define PTP_CMD_CTL_PTP_ENABLE_ BIT(2)
#define PTP_CMD_CTL_PTP_DISABLE_ BIT(1)
#define PTP_CMD_CTL_PTP_RESET_ BIT(0)
#define PTP_GENERAL_CONFIG (0x0A04)
#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
(0x7 << (1 + ((channel) << 2)))
#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1)
#define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2)
#define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3)
#define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4)
#define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5)
#define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
(((value) & 0x7) << (1 + ((channel) << 2)))
#define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2))
#define PTP_INT_STS (0x0A08)
#define PTP_INT_EN_SET (0x0A0C)
#define PTP_INT_EN_CLR (0x0A10)
#define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13)
#define PTP_INT_BIT_TX_TS_ BIT(12)
#define PTP_INT_BIT_TIMER_B_ BIT(1)
#define PTP_INT_BIT_TIMER_A_ BIT(0)
#define PTP_CLOCK_SEC (0x0A14)
#define PTP_CLOCK_NS (0x0A18)
#define PTP_CLOCK_SUBNS (0x0A1C)
#define PTP_CLOCK_RATE_ADJ (0x0A20)
#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31)
#define PTP_CLOCK_STEP_ADJ (0x0A2C)
#define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31)
#define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
#define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
#define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
#define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
#define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
#define PTP_LATENCY (0x0A5C)
#define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16)
#define PTP_LATENCY_RX_SET_(rx_latency) \
(((u32)(rx_latency)) & 0x0000FFFF)
#define PTP_CAP_INFO (0x0A60)
#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
#define PTP_TX_MOD (0x0AA4)
#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
#define PTP_TX_MOD2 (0x0AA8)
#define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
#define PTP_TX_EGRESS_SEC (0x0AAC)
#define PTP_TX_EGRESS_NS (0x0AB0)
#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
#define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
#define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
#define PTP_TX_MSG_HEADER (0x0AB4)
#define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
#define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
#define DMAC_CFG (0xC00)
#define DMAC_CFG_COAL_EN_ BIT(16)
#define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
#define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
#define DMAC_CFG_MAX_READ_REQ_SET_(val) \
((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
#define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
#define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
#define DMAC_CFG_MAX_DSPACE_64_ BIT(1)
#define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
#define DMAC_COAL_CFG (0xC04)
#define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
#define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \
((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)
#define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19)
#define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18)
#define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17)
#define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16)
#define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
#define DMAC_COAL_CFG_TX_THRES_SET_(val) \
((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
#define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
#define DMAC_COAL_CFG_RX_THRES_SET_(val) \
(((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)
#define DMAC_OBFF_CFG (0xC08)
#define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
#define DMAC_OBFF_TX_THRES_SET_(val) \
((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
#define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
#define DMAC_OBFF_RX_THRES_SET_(val) \
(((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)
#define DMAC_CMD (0xC0C)
#define DMAC_CMD_SWR_ BIT(31)
#define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel))
#define DMAC_CMD_START_T_(channel) BIT(20 + (channel))
#define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel))
#define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel))
#define DMAC_CMD_START_R_(channel) BIT(4 + (channel))
#define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
#define DMAC_INT_STS (0xC10)
#define DMAC_INT_EN_SET (0xC14)
#define DMAC_INT_EN_CLR (0xC18)
#define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel))
#define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
#define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
#define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30)
#define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
#define RX_CFG_A_RX_WB_THRES_SET_(val) \
((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)
#define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
#define RX_CFG_A_RX_PF_THRES_SET_(val) \
((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)
#define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
#define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \
((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
#define RX_CFG_A_RX_HP_WB_EN_ BIT(5)
#define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
#define RX_CFG_B_TS_ALL_RX_ BIT(29)
#define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
#define RX_CFG_B_RX_PAD_0_ (0x00000000)
#define RX_CFG_B_RX_PAD_2_ (0x02000000)
#define RX_CFG_B_RDMABL_512_ (0x00040000)
#define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
#define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
#define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
#define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
#define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
#define RX_HEAD(channel) (0xC58 + ((channel) << 6))
#define RX_TAIL(channel) (0xC5C + ((channel) << 6))
#define RX_TAIL_SET_TOP_INT_EN_ BIT(30)
#define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
#define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
#define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6)
#define RX_CFG_C_RX_INT_EN_R2C_ BIT(4)
#define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3)
#define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
#define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
#define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30)
#define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
#define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
#define TX_CFG_A_TX_PF_THRES_SET_(value) \
((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)
#define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
#define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \
((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
#define TX_CFG_A_TX_HP_WB_EN_ BIT(5)
#define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
#define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \
(((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)
#define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
#define TX_CFG_B_TDMABL_512_ (0x00040000)
#define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
#define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
#define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
#define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
#define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
#define TX_HEAD(channel) (0xD58 + ((channel) << 6))
#define TX_TAIL(channel) (0xD5C + ((channel) << 6))
#define TX_TAIL_SET_DMAC_INT_EN_ BIT(31)
#define TX_TAIL_SET_TOP_INT_EN_ BIT(30)
#define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
#define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
#define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6)
#define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5)
#define TX_CFG_C_TX_INT_EN_R2C_ BIT(4)
#define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3)
#define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
#define OTP_PWR_DN (0x1000)
#define OTP_PWR_DN_PWRDN_N_ BIT(0)
#define OTP_ADDR1 (0x1004)
#define OTP_ADDR1_15_11_MASK_ (0x1F)
#define OTP_ADDR2 (0x1008)
#define OTP_ADDR2_10_3_MASK_ (0xFF)
#define OTP_PRGM_DATA (0x1010)
#define OTP_PRGM_MODE (0x1014)
#define OTP_PRGM_MODE_BYTE_ BIT(0)
#define OTP_TST_CMD (0x1024)
#define OTP_TST_CMD_PRGVRFY_ BIT(3)
#define OTP_CMD_GO (0x1028)
#define OTP_CMD_GO_GO_ BIT(0)
#define OTP_STATUS (0x1030)
#define OTP_STATUS_BUSY_ BIT(0)
/* MAC statistics registers */
#define STAT_RX_FCS_ERRORS (0x1200)
#define STAT_RX_ALIGNMENT_ERRORS (0x1204)
#define STAT_RX_FRAGMENT_ERRORS (0x1208)
#define STAT_RX_JABBER_ERRORS (0x120C)
#define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
#define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
#define STAT_RX_DROPPED_FRAMES (0x1218)
#define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
#define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
#define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
#define STAT_RX_UNICAST_FRAMES (0x1228)
#define STAT_RX_BROADCAST_FRAMES (0x122C)
#define STAT_RX_MULTICAST_FRAMES (0x1230)
#define STAT_RX_PAUSE_FRAMES (0x1234)
#define STAT_RX_64_BYTE_FRAMES (0x1238)
#define STAT_RX_65_127_BYTE_FRAMES (0x123C)
#define STAT_RX_128_255_BYTE_FRAMES (0x1240)
#define STAT_RX_256_511_BYTES_FRAMES (0x1244)
#define STAT_RX_512_1023_BYTE_FRAMES (0x1248)
#define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)
#define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)
#define STAT_RX_TOTAL_FRAMES (0x1254)
#define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)
#define STAT_EEE_RX_LPI_TIME (0x125C)
#define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)
#define STAT_TX_FCS_ERRORS (0x1280)
#define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
#define STAT_TX_CARRIER_ERRORS (0x1288)
#define STAT_TX_BAD_BYTE_COUNT (0x128C)
#define STAT_TX_SINGLE_COLLISIONS (0x1290)
#define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
#define STAT_TX_EXCESSIVE_COLLISION (0x1298)
#define STAT_TX_LATE_COLLI
|