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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
/* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
#include "cmd.h"
#include "core.h"
#include "i2c.h"
#include "resources.h"
#define MLXSW_I2C_CIR2_BASE 0x72000
#define MLXSW_I2C_CIR_STATUS_OFF 0x18
#define MLXSW_I2C_CIR2_OFF_STATUS (MLXSW_I2C_CIR2_BASE + \
MLXSW_I2C_CIR_STATUS_OFF)
#define MLXSW_I2C_OPMOD_SHIFT 12
#define MLXSW_I2C_EVENT_BIT_SHIFT 22
#define MLXSW_I2C_GO_BIT_SHIFT 23
#define MLXSW_I2C_CIR_CTRL_STATUS_SHIFT 24
#define MLXSW_I2C_EVENT_BIT BIT(MLXSW_I2C_EVENT_BIT_SHIFT)
#define MLXSW_I2C_GO_BIT BIT(MLXSW_I2C_GO_BIT_SHIFT)
#define MLXSW_I2C_GO_OPMODE BIT(MLXSW_I2C_OPMOD_SHIFT)
#define MLXSW_I2C_SET_IMM_CMD (MLXSW_I2C_GO_OPMODE | \
MLXSW_CMD_OPCODE_QUERY_FW)
#define MLXSW_I2C_PUSH_IMM_CMD (MLXSW_I2C_GO_BIT | \
MLXSW_I2C_SET_IMM_CMD)
#define MLXSW_I2C_SET_CMD (MLXSW_CMD_OPCODE_ACCESS_REG)
#define MLXSW_I2C_PUSH_CMD (MLXSW_I2C_GO_BIT | MLXSW_I2C_SET_CMD)
#define MLXSW_I2C_TLV_HDR_SIZE 0x10
#define MLXSW_I2C_ADDR_WIDTH 4
#define MLXSW_I2C_PUSH_CMD_SIZE (MLXSW_I2C_ADDR_WIDTH + 4)
#define MLXSW_I2C_SET_EVENT_CMD (MLXSW_I2C_EVENT_BIT)
#define MLXSW_I2C_PUSH_EVENT_CMD (MLXSW_I2C_GO_BIT | \
MLXSW_I2C_SET_EVENT_CMD)
#define MLXSW_I2C_READ_SEMA_SIZE 4
#define MLXSW_I2C_PREP_SIZE (MLXSW_I2C_ADDR_WIDTH + 28)
#define MLXSW_I2C_MBOX_SIZE 20
#define MLXSW_I2C_MBOX_OUT_PARAM_OFF 12
#define MLXSW_I2C_MAX_BUFF_SIZE 32
#define MLXSW_I2C_MBOX_OFFSET_BITS 20
#define MLXSW_I2C_MBOX_SIZE_BITS 12
#define MLXSW_I2C_ADDR_BUF_SIZE 4
#define MLXSW_I2C_BLK_MAX 32
#define MLXSW_I2C_RETRY 5
#define MLXSW_I2C_TIMEOUT_MSECS 5000
#define MLXSW_I2C_MAX_DATA_SIZE 256
/**
* struct mlxsw_i2c - device private data:
* @cmd.mb_size_in: input mailbox size;
* @cmd.mb_off_in: input mailbox offset in register space;
* @cmd.mb_size_out: output mailbox size;
* @cmd.mb_off_out: output mailbox offset in register space;
* @cmd.lock: command execution lock;
* @dev: I2C device;
* @core: switch core pointer;
* @bus_info: bus info block;
*/
struct mlxsw_i2c {
struct {
u32 mb_size_in;
u32 mb_off_in;
u32 mb_size_out;
u32 mb_off_out;
struct mutex lock;
} cmd;
struct device *dev;
struct mlxsw_core *core;
struct mlxsw_bus_info bus_info;
};
#define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) { \
{ .addr = (_client)->addr, \
.buf = (_addr_buf), \
.len = MLXSW_I2C_ADDR_BUF_SIZE, \
.flags = 0 }, \
{ .addr = (_client)->addr, \
.buf = (_buf), \
.len = (_len), \
.flags = I2C_M_RD } }
#define MLXSW_I2C_WRITE_MSG(_client, _buf, _len) \
{ .addr = (_client)->addr, \
.buf = (u8 *)(_buf), \
.len = (_len), \
.flags = 0 }
/* Routine converts in and out mail boxes offset and size. */
static inline void
mlxsw_i2c_convert_mbox(struct mlxsw_i2c *mlxsw_i2c, u8 *buf)
{
u32 tmp;
/* Local in/out mailboxes: 20 bits for offset, 12 for size */
tmp = be32_to_cpup((__be32 *) buf);
mlxsw_i2c->cmd.mb_off_in = tmp &
GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
mlxsw_i2c->cmd.mb_size_in = (tmp & GENMASK(31,
MLXSW_I2C_MBOX_OFFSET_BITS)) >>
MLXSW_I2C_MBOX_OFFSET_BITS;
tmp = be32_to_cpup((__be32 *) (buf + MLXSW_I2C_ADDR_WIDTH));
mlxsw_i2c->cmd.mb_off_out = tmp &
GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
mlxsw_i2c->cmd.mb_size_out = (tmp & GENMASK(31,
MLXSW_I2C_MBOX_OFFSET_BITS)) >>
MLXSW_I2C_MBOX_OFFSET_BITS;
}
/* Routine obtains register size from mail box buffer. */
static inline int mlxsw_i2c_get_reg_size(u8 *in_mbox)
{
u16 tmp = be16_to_cpup((__be16 *) (in_mbox + MLXSW_I2C_TLV_HDR_SIZE));
return (tmp & 0x7ff) * 4 + MLXSW_I2C_TLV_HDR_SIZE;
}
/* Routine sets I2C device internal offset in the transaction buffer. */
static inline void mlxsw_i2c_set_slave_addr(u8 *buf, u32 off)
{
__be32 *val = (__be32 *) buf;
*val = htonl(off);
}
/* Routine waits until go bit is cleared. */
static int mlxsw_i2c_wait_go_bit(struct i2c_client *client,
struct mlxsw_i2c *mlxsw_i2c, u8 *p_status)
{
u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE];
u8 buf[MLXSW_I2C_READ_SEMA_SIZE];
int len = MLXSW_I2C_READ_SEMA_SIZE;
struct i2c_msg read_sema[] =
MLXSW_I2C_READ_MSG(client, addr_buf, buf, len);
bool wait_done = false;
unsigned long end;
int i = 0, err;
mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_OFF_STATUS);
end = jiffies + msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
do {
u32 ctrl;
err = i2c_transfer(client->adapter, read_sema,
ARRAY_SIZE(read_sema));
ctrl = be32_to_cpu(*(__be32 *) buf);
if (err == ARRAY_SIZE(read_sema)) {
if (!(ctrl & MLXSW_I2C_GO_BIT)) {
wait_done = true;
*p_status = ctrl >>
MLXSW_I2C_CIR_CTRL_STATUS_SHIFT;
break;
}
}
cond_resched();
} while ((time_before(jiffies, end)) || (i++ < MLXSW_I2C_RETRY));
if (wait_done) {
if (*p_status)
err = -EIO;
} else {
return -ETIMEDOUT;
}
return err > 0 ? 0 : err;
}
/* Routine posts a command to ASIC through mail box. */
static int mlxsw_i2c_write_cmd(struct i2c_client *client,
struct mlxsw_i2c *mlxsw_i2c,
int immediate)
{
__be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
0, cpu_to_be32(MLXSW_I2C_PUSH_IMM_CMD)
};
__be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
0, 0, 0, 0, 0, 0,
cpu_to_be32(client->adapter->nr & 0xffff),
cpu_to_be32(MLXSW_I2C_SET_IMM_CMD)
};
struct i2c_msg push_cmd =
MLXSW_I2C_WRITE_MSG(client, push_cmd_buf,
MLXSW_I2C_PUSH_CMD_SIZE);
struct i2c_msg prep_cmd =
MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE);
int err;
if (!immediate) {
push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_CMD);
prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_SET_CMD);
}
mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf,
MLXSW_I2C_CIR2_BASE);
mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf,
MLXSW_I2C_CIR2_OFF_STATUS);
/* Prepare Command Interface Register for transaction */
err = i2c_transfer(client->adapter, &prep_cmd, 1);
if (err < 0)
return err;
else if (err != 1)
return -EIO;
/* Write out Command Interface Register GO bit to push transaction */
err = i2c_transfer(client->adapter, &push_cmd, 1);
if (err < 0)
return err;
else if (err != 1)
return -EIO;
return 0;
}
/* Routine posts initialization command to ASIC through mail box. */
static int
mlxsw_i2c_write_init_cmd(struct i2c_client *client,
struct mlxsw_i2c *mlxsw_i2c, u16 opcode, u32 in_mod)
{
__be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
0, cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD)
};
__be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
0, 0, 0, 0, 0, 0,
cpu_to_be32(client->adapter->nr & 0xffff),
cpu_to_be32(MLXSW_I2C_SET_EVENT_CMD)
};
struct i2c_msg
|