/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2019, Mellanox Technologies */
#ifndef _DR_TYPES_
#define _DR_TYPES_
#include <linux/mlx5/driver.h>
#include <linux/refcount.h>
#include "fs_core.h"
#include "wq.h"
#include "lib/mlx5.h"
#include "mlx5_ifc_dr.h"
#include "mlx5dr.h"
#define DR_RULE_MAX_STES 17
#define DR_ACTION_MAX_STES 5
#define WIRE_PORT 0xFFFF
#define DR_STE_SVLAN 0x1
#define DR_STE_CVLAN 0x2
#define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4)
#define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
#define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
#define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg)
enum mlx5dr_icm_chunk_size {
DR_CHUNK_SIZE_1,
DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */
DR_CHUNK_SIZE_2,
DR_CHUNK_SIZE_4,
DR_CHUNK_SIZE_8,
DR_CHUNK_SIZE_16,
DR_CHUNK_SIZE_32,
DR_CHUNK_SIZE_64,
DR_CHUNK_SIZE_128,
DR_CHUNK_SIZE_256,
DR_CHUNK_SIZE_512,
DR_CHUNK_SIZE_1K,
DR_CHUNK_SIZE_2K,
DR_CHUNK_SIZE_4K,
DR_CHUNK_SIZE_8K,
DR_CHUNK_SIZE_16K,
DR_CHUNK_SIZE_32K,
DR_CHUNK_SIZE_64K,
DR_CHUNK_SIZE_128K,
DR_CHUNK_SIZE_256K,
DR_CHUNK_SIZE_512K,
DR_CHUNK_SIZE_1024K,
DR_CHUNK_SIZE_2048K,
DR_CHUNK_SIZE_MAX,
};
enum mlx5dr_icm_type {
DR_ICM_TYPE_STE,
DR_ICM_TYPE_MODIFY_ACTION,
};
static inline enum mlx5dr_icm_chunk_size
mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk)
{
chunk += 2;
if (chunk < DR_CHUNK_SIZE_MAX)
return chunk;
return DR_CHUNK_SIZE_MAX;
}
enum {
DR_STE_SIZE = 64,
DR_STE_SIZE_CTRL = 32,
DR_STE_SIZE_TAG = 16,
DR_STE_SIZE_MASK = 16,
};
enum {
DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK,
};
enum {
DR_MODIFY_ACTION_SIZE = 8,
};
enum mlx5dr_matcher_criteria {
DR_MATCHER_CRITERIA_EMPTY = 0,
DR_MATCHER_CRITERIA_OUTER = 1 << 0,
DR_MATCHER_CRITERIA_MISC = 1 << 1,
DR_MATCHER_CRITERIA_INNER = 1 << 2,
DR_MATCHER_CRITERIA_MISC2 = 1 << 3,
DR_MATCHER_CRITERIA_MISC3 = 1 << 4,
DR_MATCHER_CRITERIA_MAX = 1 << 5,
};
enum mlx5dr_action_type {
DR_ACTION_TYP_TNL_L2_TO_L2,
DR_ACTION_TYP_L2_TO_TNL_L2,
DR_ACTION_TYP_TNL_L3_TO_L2,
DR_ACTION_TYP_L2_TO_TNL_L3,
DR_ACTION_TYP_DROP,
DR_ACTION_TYP_QP,
DR_ACTION_TYP_FT,
DR_ACTION_TYP_CTR,
DR_ACTION_TYP_TAG,
DR_ACTION_TYP_MODIFY_HDR,
DR_ACTION_TYP_VPORT,
DR_ACTION_TYP_POP_VLAN,
DR_ACTION_TYP_PUSH_VLAN,
DR_ACTION_TYP_MAX,
};
enum mlx5dr_ipv {
DR_RULE_IPV4,
DR_RULE_IPV6,
DR_RULE_IPV_MAX,
};
struct mlx5dr_icm_pool;
struct mlx5dr_icm_chunk;
struct mlx5dr_icm_buddy_mem;
struct mlx5dr_ste_htbl;
struct mlx5dr_match_param;
struct mlx5dr_cmd_caps;
struct mlx5dr_matcher_rx_tx;
struct mlx5dr_ste {
u8 *hw_ste;
/* refcount: indicates the num of rules that using this ste */
u32 refcount;
/* attached to the miss_list head at each htbl entry */
struct list_head miss_list_node;
/* each rule member that uses this ste attached here */
struct list_head rule_list;
/* this ste is member of htbl */
struct mlx5dr_ste_htbl *htbl;
struct mlx5dr_ste_htbl *next_htbl;
/* this ste is part of a rule, located in ste's chain */
u8 ste_chain_location;
};
struct mlx5dr_ste_htbl_ctrl {
/* total number of valid entries belonging to this hash table. This
* includes the non collision and collision entries
*/
unsigned int num_of_valid_entries;
/* total number of collisions entries attached to this table */
unsigned int num_of_collisions;
unsigned int increase_threshold;
u8 may_grow:1;
};
struct mlx5dr_ste_htbl {
u8 lu_type;
u16 byte_mask;
u32 refcount;
struct mlx5dr_icm_chunk *chunk;
struct mlx5dr_ste *ste_arr;
u8 *hw_ste_arr;
struct list_head *mis