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|
// SPDX-License-Identifier: GPL-2.0
/*
* Lantiq / Intel PMAC driver for XRX200 SoCs
*
* Copyright (C) 2010 Lantiq Deutschland
* Copyright (C) 2012 John Crispin <john@phrozen.org>
* Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de>
*/
#include <linux/etherdevice.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_net.h>
#include <linux/of_platform.h>
#include <xway_dma.h>
/* DMA */
#define XRX200_DMA_DATA_LEN 0x600
#define XRX200_DMA_RX 0
#define XRX200_DMA_TX 1
/* cpu port mac */
#define PMAC_RX_IPG 0x0024
#define PMAC_RX_IPG_MASK 0xf
#define PMAC_HD_CTL 0x0000
/* Add Ethernet header to packets from DMA to PMAC */
#define PMAC_HD_CTL_ADD BIT(0)
/* Add VLAN tag to Packets from DMA to PMAC */
#define PMAC_HD_CTL_TAG BIT(1)
/* Add CRC to packets from DMA to PMAC */
#define PMAC_HD_CTL_AC BIT(2)
/* Add status header to packets from PMAC to DMA */
#define PMAC_HD_CTL_AS BIT(3)
/* Remove CRC from packets from PMAC to DMA */
#define PMAC_HD_CTL_RC BIT(4)
/* Remove Layer-2 header from packets from PMAC to DMA */
#define PMAC_HD_CTL_RL2 BIT(5)
/* Status header is present from DMA to PMAC */
#define PMAC_HD_CTL_RXSH BIT(6)
/* Add special tag from PMAC to switch */
#define PMAC_HD_CTL_AST BIT(7)
/* Remove specail Tag from PMAC to DMA */
#define PMAC_HD_CTL_RST BIT(8)
/* Check CRC from DMA to PMAC */
#define PMAC_HD_CTL_CCRC BIT(9)
/* Enable reaction to Pause frames in the PMAC */
#define PMAC_HD_CTL_FC BIT(10)
struct xrx200_chan {
int tx_free;
struct napi_struct napi;
struct ltq_dma_channel dma;
struct sk_buff *skb[LTQ_DESC_NUM];
struct xrx200_priv *priv;
};
struct xrx200_priv {
struct clk *clk;
struct xrx200_chan chan_tx;
struct xrx200_chan chan_rx;
struct net_device *net_dev;
struct device *dev;
__iomem void *pmac_reg;
};
static u32 xrx200_pmac_r32(struct xrx200_priv *priv, u32 offset)
{
return __raw_readl(priv->pmac_reg + offset);
}
static void xrx200_pmac_w32(struct xrx200_priv *priv, u32 val, u32 offset)
{
__raw_writel(val, priv->pmac_reg + offset);
}
static void xrx200_pmac_mask(struct xrx200_priv *priv, u32 clear, u32 set,
u32 offset)
{
u32 val = xrx200_pmac_r32(priv, offset);
val &= ~(clear);
val |= set;
xrx200_pmac_w32(priv, val, offset);
}
/* drop all the packets from the DMA ring */
static void xrx200_flush_dma(struct xrx200_chan *ch)
{
int i;
for (i = 0; i < LTQ_DESC_NUM; i++) {
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
break;
desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
XRX200_DMA_DATA_LEN;
ch->dma.desc++;
ch->dma.desc %= LTQ_DESC_NUM;
}
}
static int xrx200_open(struct net_device *net_dev)
{
struct xrx200_priv *priv = netdev_priv(net_dev);
napi_enable(&priv->chan_tx.napi);
ltq_dma_open(&priv->chan_tx.dma);
ltq_dma_enable_irq(&priv->chan_tx.dma);
napi_enable(&priv->chan_rx.napi);
ltq_dma_open(&priv->chan_rx.dma);
/* The boot loader does not always deactivate the receiving of frames
* on the ports and then some packets queue up in the PPE buffers.
* They already passed the PMAC so they do not have the tags
* configured here. Read the these packets here and drop them.
* The HW should have written them into memory after 10us
*/
usleep_range(20, 40);
xrx200_flush_dma(&priv->chan_rx);
ltq_dma_enable_irq(&priv->chan_rx.dma);
netif_wake_queue(net_dev);
return 0;
}
static int xrx200_close(struct net_device *net_dev)
{
struct xrx200_priv *priv = netdev_priv(net_dev);
netif_stop_queue(net_dev);
napi_disable(&priv->chan_rx.napi);
ltq_dma_close(&priv->chan_rx.dma);
napi_disable(&priv->chan_tx.napi);
ltq_dma_close(&priv->chan_tx.dma);
return 0;
}
static int xrx200_alloc_skb(struct xrx200_chan *ch)
{
int ret = 0;
ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev,
XRX200_DMA_DATA_LEN);
if (!ch->skb[ch->dma.desc]) {
ret = -ENOMEM;
goto skip;
}
ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->priv->dev,
ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
DMA_FROM_DEVICE);
if (unlikely(dma_mapping_error(ch->priv->dev,
ch->dma.desc_base[ch->dma.desc].addr))) {
dev_kfree_skb_any(ch->skb[ch->dma.desc]);
ret = -ENOMEM;
goto skip;
}
skip:
ch->dma.desc_base[ch->dma.desc].ctl =
LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
XRX200_DMA_DATA_LEN;
return ret;
}
static int xrx200_hw_receive(struct xrx200_chan *ch)
{
struct xrx200_priv *priv = ch->priv;
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
struct sk_buff *skb = ch->skb[ch->dma.desc];
int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
struct net_device *net_dev = priv->net_dev;
int ret;
ret = xrx200_alloc_skb(ch);
ch->dma.desc++;
ch->dma.desc %= LTQ_DESC_NUM;
if (ret) {
netdev_err(net_dev, "failed to allocate new rx buffer\n");
return ret;
}
skb_put(skb, len);
skb->protocol = eth_type_trans(skb, net_dev);
netif_receive_skb(skb);
net_dev->stats.rx_packets++;
net_dev->stats.rx_bytes += len - ETH_FCS_LEN;
return 0;
}
static int xrx200_poll_rx(struct napi_struct *napi, int budget)
{
struct xrx200_chan *ch = container_of(napi,
struct xrx200_chan, napi);
int rx = 0;
int ret;
while (rx < budget) {
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
ret = xrx200_hw_receive(ch);
if (ret)
return ret;
rx++;
} else {
break;
}
}
if (rx < budget) {
napi_complete(&ch->napi);
ltq_dma_enable_irq(&ch->dma);
}
return rx;
}
static int xrx200_tx_housekeeping(struct napi_struct *napi, int budget)
{
struct xrx200_chan *ch = container_of(napi,
struct xrx200_chan, napi);
struct net_device *net_dev = ch->priv->net_dev;
int pkts = 0;
int bytes = 0;
while (pkts < budget) {
struct
|