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|
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019 Intel Corporation */
#include "igc.h"
#include <linux/module.h>
#include <linux/device.h>
#include <linux/pci.h>
#include <linux/ptp_classify.h>
#include <linux/clocksource.h>
#define INCVALUE_MASK 0x7fffffff
#define ISGN 0x80000000
#define IGC_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
#define IGC_PTP_TX_TIMEOUT (HZ * 15)
/* SYSTIM read access for I225 */
static void igc_ptp_read_i225(struct igc_adapter *adapter,
struct timespec64 *ts)
{
struct igc_hw *hw = &adapter->hw;
u32 sec, nsec;
/* The timestamp latches on lowest register read. For I210/I211, the
* lowest register is SYSTIMR. Since we only need to provide nanosecond
* resolution, we can ignore it.
*/
rd32(IGC_SYSTIMR);
nsec = rd32(IGC_SYSTIML);
sec = rd32(IGC_SYSTIMH);
ts->tv_sec = sec;
ts->tv_nsec = nsec;
}
static void igc_ptp_write_i225(struct igc_adapter *adapter,
const struct timespec64 *ts)
{
struct igc_hw *hw = &adapter->hw;
/* Writing the SYSTIMR register is not necessary as it only
* provides sub-nanosecond resolution.
*/
wr32(IGC_SYSTIML, ts->tv_nsec);
wr32(IGC_SYSTIMH, ts->tv_sec);
}
static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
{
struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
ptp_caps);
struct igc_hw *hw = &igc->hw;
int neg_adj = 0;
u64 rate;
u32 inca;
if (scaled_ppm < 0) {
neg_adj = 1;
scaled_ppm = -scaled_ppm;
}
rate = scaled_ppm;
rate <<= 14;
rate = div_u64(rate, 78125);
inca = rate & INCVALUE_MASK;
if (neg_adj)
inca |= ISGN;
wr32(IGC_TIMINCA, inca);
return 0;
}
static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
{
struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
ptp_caps);
struct timespec64 now, then = ns_to_timespec64(delta);
unsigned long flags;
spin_lock_irqsave(&igc->tmreg_lock, flags);
igc_ptp_read_i225(igc, &now);
now = timespec64_add(now, then);
igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
spin_unlock_irqrestore(&igc->tmreg_lock, flags);
return 0;
}
static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
struct timespec64 *ts,
struct ptp_system_timestamp *sts)
{
struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
ptp_caps);
struct igc_hw *hw = &igc->hw;
unsigned long flags;
spin_lock_irqsave(&igc->tmreg_lock, flags);
ptp_read_system_prets(sts);
rd32(IGC_SYSTIMR);
ptp_read_system_postts(sts);
ts->tv_nsec = rd32(IGC_SYSTIML);
ts->tv_sec = rd32(IGC_SYSTIMH);
spin_unlock_irqrestore(&igc->tmreg_lock, flags);
return 0;
}
static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
const struct timespec64 *ts)
{
struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
ptp_caps);
unsigned long flags;
spin_lock_irqsave(&igc->tmreg_lock, flags);
igc_ptp_write_i225(igc, ts);
spin_unlock_irqrestore(&igc->tmreg_lock, flags);
return 0;
}
static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on)
{
return -EOPNOTSUPP;
}
/**
* igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
* @adapter: board private structure
* @hwtstamps: timestamp structure to update
* @systim: unsigned 64bit system time value
*
* We need to convert the system time value stored in the RX/TXSTMP registers
* into a hwtstamp which can be used by the upper level timestamping functions.
**/
static void igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
struct skb_shared_hwtstamps *hwtstamps,
u64 systim)
{
switch (adapter->hw.mac.type) {
case igc_i225:
memset(hwtstamps, 0, sizeof(*hwtstamps));
/* Upper 32 bits contain s, lower 32 bits contain ns. */
hwtstamps->hwtstamp = ktime_set(systim >> 32,
systim & 0xFFFFFFFF);
break;
default:
break;
}
}
/**
* igc_ptp_rx_pktstamp - retrieve Rx per packet timestamp
* @q_vector: Pointer to interrupt specific structure
* @va: Pointer to address containing Rx buffer
* @skb: Buffer containing timestamp and packet
*
* This function is meant to retrieve the first timestamp from the
* first buffer of an incoming frame. The value is stored in little
* endian format starting on byte 0. There's a second timestamp
* starting on byte 8.
**/
void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va,
struct sk_buff *skb)
{
struct igc_adapter *adapter = q_vector->adapter;
__le64 *regval = (__le64 *)va;
int adjust = 0;
/* The timestamp is recorded in little endian format.
* DWORD: | 0 | 1 | 2 | 3
* Field: | Timer0 Low | Timer0 High | Timer1 Low | Timer1 High
*/
igc_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb),
le64_to_cpu(regval[0]));
/* adjust timestamp for the RX latency based on link speed */
if (adapter->hw.mac.type == igc_i225) {
switch (adapter->link_speed) {
case SPEED_10:
adjust = IGC_I225_RX_LATENCY_10;
break;
case SPEED_100:
adjust = IGC_I225_RX_LATENCY_100;
break;
case SPEED_1000:
adjust = IGC_I225_RX_LATENCY_1000;
break;
case SPEED_2500:
adjust = IGC_I225_RX_LATENCY_2500;
break;
}
}
skb_hwtstamps(skb)->hwtstamp =
ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
}
/**
* igc_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
* @q_vector: Pointer to interrupt specific structure
* @skb: Buffer containing timestamp and packet
*
* This function is meant to retrieve a timestamp from the internal registers
* of the adapter and store it in the skb.
*/
void igc_ptp_rx_rgtstamp(struct igc_q_vector *q_vector,
struct sk_buff *skb)
{
struct igc_adapter *adapter = q_vector->adapter;
struct igc_hw *hw = &adapter->hw;
u64 regval;
/* If this bit is set, then the RX registers contain the time
* stamp. No other packet will be time stamped until we read
* these registers, so read
|