/* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
*
* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/pci.h>
#include <linux/ptp_classify.h>
#include "igb.h"
#define INCVALUE_MASK 0x7fffffff
#define ISGN 0x80000000
/* The 82580 timesync updates the system timer every 8ns by 8ns,
* and this update value cannot be reprogrammed.
*
* Neither the 82576 nor the 82580 offer registers wide enough to hold
* nanoseconds time values for very long. For the 82580, SYSTIM always
* counts nanoseconds, but the upper 24 bits are not available. The
* frequency is adjusted by changing the 32 bit fractional nanoseconds
* register, TIMINCA.
*
* For the 82576, the SYSTIM register time unit is affect by the
* choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
* field are needed to provide the nominal 16 nanosecond period,
* leaving 19 bits for fractional nanoseconds.
*
* We scale the NIC clock cycle by a large factor so that relatively
* small clock corrections can be added or subtracted at each clock
* tick. The drawbacks of a large factor are a) that the clock
* register overflows more quickly (not such a big deal) and b) that
* the increment per tick has to fit into 24 bits. As a result we
* need to use a shift of 19 so we can fit a value of 16 into the
* TIMINCA register.
*
*
* SYSTIMH SYSTIML
* +--------------+ +---+---+------+
* 82576 | 32 | | 8 | 5 | 19 |
* +--------------+ +---+---+------+
* \________ 45 bits _______/ fract
*
* +----------+---+ +--------------+
* 82580 | 24 | 8 | | 32 |
* +----------+---+ +--------------+
* reserved \______ 40 bits _____/
*
*
* The 45 bit 82576 SYSTIM overflows every
* 2^45 * 10^-9 / 3600 = 9.77 hours.
*
* The 40 bit 82580 SYSTIM overflows every
* 2^40 * 10^-9 / 60 = 18.3 minutes.
*/
#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
#define IGB_PTP_TX_TIMEOUT (HZ * 15)
#define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
#define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
#define IGB_NBITS_82580 40
static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
/* SYSTIM read access for the 82576 */
static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
{
struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
struct e1000_hw *hw = &igb->hw;
u64 val;
u32 lo, hi;
lo = rd32(E1000_SYSTIML);
hi = rd32(E1000_SYSTIMH);
val = ((u64) hi) << 32;
val |= lo;
return val;
}
/* SYSTIM read access for the 82580 */
static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
{
struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
struct e1000_hw *hw = &igb->hw;
u32 lo, hi;
u64 val;
/* The timestamp latches on lowest register read. For the 82580
* the lowest register is SYSTIMR instead of SYSTIML. However we only
* need to provide nanosecond resolution, so we just ignore it.
*/
rd32(E1000_SYSTIMR);
lo = rd32(E1000_SYSTIML);
hi = rd32(E1000_SYSTIMH);
val = ((u64) hi) << 32;
val |= lo;
return val;
}
/* SYSTIM read access for I210/I211 */
static void igb_ptp_read_i210(struct igb_adapter *adapter,
struct timespec64 *ts)
{
struct e1000_hw *hw = &adapter