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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2013 - 2018 Intel Corporation. */
#ifndef _IAVF_TYPE_H_
#define _IAVF_TYPE_H_
#include "iavf_status.h"
#include "iavf_osdep.h"
#include "iavf_register.h"
#include "iavf_adminq.h"
#include "iavf_devids.h"
#define IAVF_RXQ_CTX_DBUFF_SHIFT 7
/* IAVF_MASK is a macro used on 32 bit registers */
#define IAVF_MASK(mask, shift) ((u32)(mask) << (shift))
#define IAVF_MAX_VSI_QP 16
#define IAVF_MAX_VF_VSI 3
#define IAVF_MAX_CHAINED_RX_BUFFERS 5
/* forward declaration */
struct iavf_hw;
typedef void (*I40E_ADMINQ_CALLBACK)(struct iavf_hw *, struct i40e_aq_desc *);
/* Data type manipulation macros. */
#define IAVF_DESC_UNUSED(R) \
((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
(R)->next_to_clean - (R)->next_to_use - 1)
/* bitfields for Tx queue mapping in QTX_CTL */
#define IAVF_QTX_CTL_VF_QUEUE 0x0
#define IAVF_QTX_CTL_VM_QUEUE 0x1
#define IAVF_QTX_CTL_PF_QUEUE 0x2
/* debug masks - set these bits in hw->debug_mask to control output */
enum iavf_debug_mask {
IAVF_DEBUG_INIT = 0x00000001,
IAVF_DEBUG_RELEASE = 0x00000002,
IAVF_DEBUG_LINK = 0x00000010,
IAVF_DEBUG_PHY = 0x00000020,
IAVF_DEBUG_HMC = 0x00000040,
IAVF_DEBUG_NVM = 0x00000080,
IAVF_DEBUG_LAN = 0x00000100,
IAVF_DEBUG_FLOW = 0x00000200,
IAVF_DEBUG_DCB = 0x00000400,
IAVF_DEBUG_DIAG = 0x00000800,
IAVF_DEBUG_FD = 0x00001000,
IAVF_DEBUG_PACKAGE = 0x00002000,
IAVF_DEBUG_AQ_MESSAGE = 0x01000000,
IAVF_DEBUG_AQ_DESCRIPTOR = 0x02000000,
IAVF_DEBUG_AQ_DESC_BUFFER = 0x04000000,
IAVF_DEBUG_AQ_COMMAND = 0x06000000,
IAVF_DEBUG_AQ = 0x0F000000,
IAVF_DEBUG_USER = 0xF0000000,
IAVF_DEBUG_ALL = 0xFFFFFFFF
};
/* These are structs for managing the hardware information and the operations.
* The structures of function pointers are filled out at init time when we
* know for sure exactly which hardware we're working with. This gives us the
* flexibility of using the same main driver code but adapting to slightly
* different hardware needs as new parts are developed. For this architecture,
* the Firmware and AdminQ are intended to insulate the driver from most of the
* future changes, but these structures will also do part of the job.
*/
enum iavf_mac_type {
IAVF_MAC_UNKNOWN = 0,
IAVF_MAC_XL710,
IAVF_MAC_VF,
IAVF_MAC_X722,
IAVF_MAC_X722_VF,
IAVF_MAC_GENERIC,
};
enum iavf_vsi_type {
IAVF_VSI_MAIN = 0,
IAVF_VSI_VMDQ1 = 1,
IAVF_VSI_VMDQ2 = 2,
IAVF_VSI_CTRL = 3,
IAVF_VSI_FCOE = 4,
IAVF_VSI_MIRROR = 5,
IAVF_VSI_SRIOV = 6,
IAVF_VSI_FDIR = 7,
IAVF_VSI_TYPE_UNKNOWN
};
enum iavf_queue_type {
IAVF_QUEUE_TYPE_RX = 0,
IAVF_QUEUE_TYPE_TX,
IAVF_QUEUE_TYPE_PE_CEQ,
IAVF_QUEUE_TYPE_UNKNOWN
};
#define IAVF_HW_CAP_MAX_GPIO 30
/* Capabilities of a PF or a VF or the whole device */
struct iavf_hw_capabilities {
bool dcb;
bool fcoe;
u32 num_vsis;
u32 num_rx_qp;
u32 num_tx_qp;
u32 base_queue;
u32 num_msix_vectors_vf;
};
struct iavf_mac_info {
enum iavf_mac_type type;
u8 addr[ETH_ALEN];
u8 perm_addr[ETH_ALEN];
u8 san_addr[ETH_ALEN];
u16 max_fcoeq;
};
/* PCI bus types */
enum iavf_bus_type {
iavf_bus_type_unknown = 0,
iavf_bus_type_pci,
iavf_bus_type_pcix,
iavf_bus_type_pci_express,
iavf_bus_type_reserved
};
/* PCI bus speeds */
enum iavf_bus_speed {
iavf_bus_speed_unknown = 0,
iavf_bus_speed_33 = 33,
iavf_bus_speed_66 = 66,
iavf_bus_speed_100 = 100,
iavf_bus_speed_120 = 120,
iavf_bus_speed_133 = 133,
iavf_bus_speed_2500 = 2500,
iavf_bus_speed_5000 = 5000,
iavf_bus_speed_8000 = 8000,
iavf_bus_speed_reserved
};
/* PCI bus widths */
enum iavf_bus_width {
iavf_bus_width_unknown = 0,
iavf_bus_width_pcie_x1 = 1,
iavf_bus_width_pcie_x2 = 2,
iavf_bus_width_pcie_x4 = 4,
iavf_bus_width_pcie_x8 = 8,
iavf_bus_width_32 = 32,
iavf_bus_width_64 = 64,
iavf_bus_width_reserved
};
/* Bus parameters */
struct iavf_bus_info {
enum iavf_bus_speed speed;
enum iavf_bus_width width;
enum iavf_bus_type type;
u16 func;
u16 device;
u16 lan_id;
u16 bus_id;
};
#define IAVF_MAX_USER_PRIORITY 8
/* Port hardware description */
struct iavf_hw {
u8 __iomem *hw_addr;
void *back;
/* subsystem structs */
struct iavf_mac_info mac;
struct iavf_bus_info bus;
/* pci info */
u16 device_id;
u16 vendor_id;
u16 subsystem_device_id;
u16 subsystem_vendor_id;
u8 revision_id;
/* capabilities for entire device and PCI func */
struct iavf_hw_capabilities dev_caps;
/* Admin Queue info */
struct iavf_adminq_info aq;
/* debug mask */
u32 debug_mask;
char err_str[16];
};
struct iavf_driver_version {
u8 major_version;
u8 minor_version;
u8 build_version;
u8 subbuild_version;
u8 driver_string[32];
};
/* RX Descriptors */
union iavf_16byte_rx_desc {
struct {
__le64 pkt_addr; /* Packet buffer address */
__le64 hdr_addr; /* Header buffer address */
} read;
struct {
struct {
struct {
union {
__le16 mirroring_status;
__le16 fcoe_ctx_id;
} mirr_fcoe;
__le16 l2tag1;
} lo_dword;
union {
__le32 rss; /* RSS Hash */
__le32 fd_id; /* Flow director filter id */
__le32 fcoe_param; /* FCoE DDP Context id */
} hi_dword;
} qword0;
struct {
/* ext status/error/pktype/length */
__le64 status_error_len;
} qword1;
} wb; /* writeback */
};
union iavf_32byte_rx_desc {
struct {
__le64 pkt_addr; /* Packet buffer address */
__le64 hdr_addr; /* Header buffer address */
/* bit 0 of hdr_buffer_addr is DD bit */
__le64 rsvd1;
__le64 rsvd2;
} read;
struct {
struct {
struct {
union {
__le16 mirroring_status;
__le16 fcoe_ctx_id;
} mirr_fcoe;
__le16 l2tag1;
} lo_dword;
union {
__le32 rss; /* RSS Hash */
__le32 fcoe_param; /* FCoE DDP Context id */
/* Flow director filter id in case of
* Programming status desc WB
*/
__le32 fd_id;
} hi_dword;
} qword0;
struct {
/* status/error/pktype/length */
__le64 status_error_len;
} qword1;
struct {
__le16 ext_status; /* extended status */
__le16 rsvd;
__le16 l2tag2_1;
__le16 l2tag2_2;
} qword2;
struct {
union {
__le32 flex_bytes_lo;
__le32 pe_status;
} lo_dword;
union {
__le32 flex_bytes_hi;
__le32 fd_id;
} hi_dword;
} qword3;
} wb; /* writeback */
};
enum iavf_rx_desc_status_bits {
/* Note: These are predefined bit offsets */
IAVF_RX_DESC_STATUS_DD_SHIFT = 0,
IAVF_RX_DESC_STATUS_EOF_SHIFT = 1,
IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
IAVF_RX_DESC_STATUS_L3L4P_SHIFT = 3,
IAVF_RX_DESC_STATUS_CRCP_SHIFT = 4,
IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
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