path: root/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 */

#ifndef _DSAF_REG_H_
#define _DSAF_REG_H_

#include <linux/regmap.h>
#define HNS_DEBUG_RING_IRQ_IDX		0
#define HNS_SERVICE_RING_IRQ_IDX	59
#define HNSV2_SERVICE_RING_IRQ_IDX	25

#define DSAF_MAX_PORT_NUM	6
#define DSAF_MAX_VM_NUM		128

#define DSAF_COMM_DEV_NUM	1
#define DSAF_PPE_INODE_BASE	6
#define DSAF_DEBUG_NW_NUM	2
#define DSAF_SERVICE_NW_NUM	6
#define DSAF_COMM_CHN		DSAF_SERVICE_NW_NUM
#define DSAF_GE_NUM		((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM))
#define DSAF_XGE_NUM		DSAF_SERVICE_NW_NUM
#define DSAF_PORT_TYPE_NUM 3
#define DSAF_NODE_NUM		18
#define DSAF_XOD_BIG_NUM	DSAF_NODE_NUM
#define DSAF_SBM_NUM		DSAF_NODE_NUM
#define DSAFV2_SBM_NUM		8
#define DSAFV2_SBM_XGE_CHN    6
#define DSAFV2_SBM_PPE_CHN    1
#define DASFV2_ROCEE_CRD_NUM  1

#define DSAF_VOQ_NUM		DSAF_NODE_NUM
#define DSAF_INODE_NUM		DSAF_NODE_NUM
#define DSAF_XOD_NUM		8
#define DSAF_TBL_NUM		8
#define DSAF_SW_PORT_NUM	8
#define DSAF_TOTAL_QUEUE_NUM	129

/* reserved a tcam entry for each port to support promisc by fuzzy match */
#define DSAFV2_MAC_FUZZY_TCAM_NUM    DSAF_MAX_PORT_NUM

#define DSAF_TCAM_SUM		512
#define DSAF_LINE_SUM		(2048 * 14)

#define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG			0x100
#define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG		0x180
#define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG		0x184
#define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG		0x188
#define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG		0x18C
#define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG		0x190
#define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG		0x194
#define DSAF_SUB_SC_DSAF_CLK_EN_REG			0x300
#define DSAF_SUB_SC_DSAF_CLK_DIS_REG			0x304
#define DSAF_SUB_SC_NT_CLK_EN_REG			0x308
#define DSAF_SUB_SC_NT_CLK_DIS_REG			0x30C
#define DSAF_SUB_SC_XGE_CLK_EN_REG			0x310
#define DSAF_SUB_SC_XGE_CLK_DIS_REG			0x314
#define DSAF_SUB_SC_GE_CLK_EN_REG			0x318
#define DSAF_SUB_SC_GE_CLK_DIS_REG			0x31C
#define DSAF_SUB_SC_PPE_CLK_EN_REG			0x320
#define DSAF_SUB_SC_PPE_CLK_DIS_REG			0x324
#define DSAF_SUB_SC_RCB_PPE_COM_CLK_EN_REG		0x350
#define DSAF_SUB_SC_RCB_PPE_COM_CLK_DIS_REG		0x354
#define DSAF_SUB_SC_XBAR_RESET_REQ_REG			0xA00
#define DSAF_SUB_SC_XBAR_RESET_DREQ_REG			0xA04
#define DSAF_SUB_SC_NT_RESET_REQ_REG			0xA08
#define DSAF_SUB_SC_NT_RESET_DREQ_REG			0xA0C
#define DSAF_SUB_SC_XGE_RESET_REQ_REG			0xA10
#define DSAF_SUB_SC_XGE_RESET_DREQ_REG			0xA14
#define DSAF_SUB_SC_GE_RESET_REQ0_REG			0xA18
#define DSAF_SUB_SC_GE_RESET_DREQ0_REG			0xA1C
#define DSAF_SUB_SC_GE_RESET_REQ1_REG			0xA20
#define DSAF_SUB_SC_GE_RESET_DREQ1_REG			0xA24
#define DSAF_SUB_SC_PPE_RESET_REQ_REG			0xA48
#define DSAF_SUB_SC_PPE_RESET_DREQ_REG			0xA4C
#define DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG		0xA88
#define DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG		0xA8C
#define DSAF_SUB_SC_DSAF_RESET_REQ_REG			0xAA8
#define DSAF_SUB_SC_DSAF_RESET_DREQ_REG			0xAAC
#define DSAF_SUB_SC_ROCEE_RESET_REQ_REG			0xA50
#define DSAF_SUB_SC_ROCEE_RESET_DREQ_REG		0xA54
#define DSAF_SUB_SC_ROCEE_CLK_DIS_REG			0x32C
#define DSAF_SUB_SC_ROCEE_CLK_EN_REG			0x328
#define DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG		0x2060
#define DSAF_SUB_SC_TCAM_MBIST_EN_REG			0x2300
#define DSAF_SUB_SC_DSAF_CLK_ST_REG			0x5300
#define DSAF_SUB_SC_NT_CLK_ST_REG			0x5304
#define DSAF_SUB_SC_XGE_CLK_ST_REG			0x5308
#define DSAF_SUB_SC_GE_CLK_ST_REG			0x530C
#define DSAF_SUB_SC_PPE_CLK_ST_REG			0x5310
#define DSAF_SUB_SC_ROCEE_CLK_ST_REG			0x5314
#define DSAF_SUB_SC_CPU_CLK_ST_REG			0x5318
#define DSAF_SUB_SC_RCB_PPE_COM_CLK_ST_REG		0x5328
#define DSAF_SUB_SC_XBAR_RESET_ST_REG			0x5A00
#define DSAF_SUB_SC_NT_RESET_ST_REG			0x5A04
#define DSAF_SUB_SC_XGE_RESET_ST_REG			0x5A08
#define DSAF_SUB_SC_GE_RESET_ST0_REG			0x5A0C
#define DSAF_SUB_SC_GE_RESET_ST1_REG			0x5A10
#define DSAF_SUB_SC_PPE_RESET_ST_REG			0x5A24
#define DSAF_SUB_SC_RCB_PPE_COM_RESET_ST_REG		0x5A44

/*serdes offset**/
#define HNS_MAC_HILINK3_REG DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG
#define HNS_MAC_HILINK4_REG DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG
#define HNS_MAC_HILINK3V2_REG DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG
#define HNS_MAC_HILINK4V2_REG DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG
#define HNS_MAC_LANE0_CTLEDFE_REG 0x000BFFCCULL
#define HNS_MAC_LANE1_CTLEDFE_REG 0x000BFFBCULL
#define HNS_MAC_LANE2_CTLEDFE_REG 0x000BFFACULL
#define HNS_MAC_LANE3_CTLEDFE_REG 0x000BFF9CULL
#define HNS_MAC_LANE0_STATE_REG 0x000BFFD4ULL
#define HNS_MAC_LANE1_STATE_REG 0x000BFFC4ULL
#define HNS_MAC_LANE2_STATE_REG 0x000BFFB4ULL
#define HNS_MAC_LANE3_STATE_REG 0x000BFFA4ULL

#define HILINK_RESET_TIMOUT 10000

#define DSAF_SRAM_INIT_OVER_0_REG	0x0
#define DSAF_CFG_0_REG			0x4
#define DSAF_ECC_ERR_INVERT_0_REG	0x8
#define DSAF_ABNORMAL_TIMEOUT_0_REG	0x1C
#define DSAF_FSM_TIMEOUT_0_REG		0x20
#define DSAF_DSA_REG_CNT_CLR_CE_REG	0x2C
#define DSAF_DSA_SBM_INF_FIFO_THRD_REG	0x30
#define DSAF_DSA_SRAM_1BIT_ECC_SEL_REG	0x34
#define DSAF_DSA_SRAM_1BIT_ECC_CNT_REG	0x38
#define DSAF_PFC_EN_0_REG		0x50
#define DSAF_PFC_UNIT_CNT_0_REG		0x70
#define DSAF_XGE_INT_MSK_0_REG		0x100
#define DSAF_PPE_INT_MSK_0_REG		0x120
#define DSAF_ROCEE_INT_MSK_0_REG	0x140
#define DSAF_XGE_INT_SRC_0_REG		0x160
#define DSAF_PPE_INT_SRC_0_REG		0x180
#define DSAF_ROCEE_INT_SRC_0_REG	0x1A0
#define DSAF_XGE_INT_STS_0_REG		0x1C0
#define DSAF_PPE_INT_STS_0_REG		0x1E0
#define DSAF_ROCEE_INT_STS_0_REG	0x200
#define DSAFV2_SERDES_LBK_0_REG         0x220
#define DSAF_PAUSE_CFG_REG		0x240
#define DSAF_ROCE_PORT_MAP_REG		0x2A0
#define DSAF_ROCE_SL_MAP_REG		0x2A4
#define DSAF_PPE_QID_CFG_0_REG		0x300
#define DSAF_SW_PORT_TYPE_0_REG		0x320
#define DSAF_STP_PORT_TYPE_0_REG	0x340
#define DSAF_MIX_DEF_QID_0_REG		0x360
#define DSAF_PORT_DEF_VLAN_0_REG	0x380
#define DSAF_VM_DEF_VLAN_0_REG		0x400

#define DSAF_INODE_CUT_THROUGH_CFG_0_REG	0x1000
#define DSAF_INODE_ECC_INVERT_EN_0_REG		0x1008
#define DSAF_INODE_ECC_ERR_ADDR_0_REG		0x100C
#define DSAF_INODE_IN_PORT_NUM_0_REG		0x1018
#define DSAF_INODE_PRI_TC_CFG_0_REG		0x101C
#define DSAF_INODE_BP_STATUS_0_REG		0x1020
#define DSAF_INODE_PAD_DISCARD_NUM_0_REG	0x1028
#define DSAF_INODE_FINAL_IN_MAN_NUM_0_REG	0x102C
#define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG	0x1030
#define DSAF_INODE_SBM_PID_NUM_0_REG		0x1038
#define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG	0x103C
#define DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG	0x1024
#define DSAF_INODE_SBM_RELS_NUM_0_REG		0x104C
#define DSAF_INODE_SBM_DROP_NUM_0_REG		0x1050
#define DSAF_INODE_CRC_FALSE_NUM_0_REG		0x1054
#define DSAF_INODE_BP_DISCARD_NUM_0_REG		0x1058
#define DSAF_INODE_RSLT_DISCARD_NUM_0_REG	0x105C
#define DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG	0x1060
#define DSAF_INODE_VOQ_OVER_NUM_0_REG		0x1068
#define DSAF_INODE_BD_SAVE_STATUS_0_REG		0x1900
#define DSAF_INODE_BD_ORDER_STATUS_0_REG	0x1950
#define DSAF_INODE_SW_VLAN_TAG_DISC_0_REG	0x1A00
#define DSAF_INODE_IN_DATA_STP_DISC_0_REG	0x1A50
#define DSAF_INODE_GE_FC_EN_0_REG		0x1B00
#define DSAF_INODE_VC0_IN_PKT_NUM_0_REG		0x1B50
#define DSAF_INODE_VC1_IN_PKT_NUM_0_REG		0x103C
#define DSAF_INODE_IN_PRIO_PAUSE_BASE_REG	0x1C00
#define DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET	0x100
#define DSAF_INODE_IN_PRIO_PAUSE_OFFSET		0x50

#define DSAF_SBM_CFG_REG_0_REG			0x2000
#define DSAF_SBM_BP_CFG_0_XGE_REG_0_REG		0x2004
#define DSAF_SBM_BP_CFG_0_PPE_REG_0_REG		0x2304
#define DSAF_SBM_BP_CFG_0_ROCEE_REG_0_REG	0x2604
#define DSAF_SBM_BP_CFG_1_REG_0_REG		0x2008
#define DSAF_SBM_BP_CFG_2_XGE_REG_0_REG		0x200C
#define DSAF_SBM_BP_CFG_2_PPE_REG_0_REG		0x230C
#define DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG	0x260C
#define DSAF_SBM_ROCEE_CFG_REG_REG		0x2380
#define DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG	0x238C
#define DSAF_SBM_FREE_CNT_0_0_REG		0x2010
#define DSAF_SBM_FREE_CNT_1_0_REG		0x2014
#define DSAF_SBM_BP_CNT_0_0_REG			0x2018
#define DSAF_SBM_BP_CNT_1_0_REG			0x201C
#define DSAF_SBM_BP_CNT_2_0_REG			0x2020
#define DSAF_SBM_BP_CNT_3_0_REG			0x2024
#define DSAF_SBM_INER_ST_0_REG			0x2028
#define DSAF_SBM_MIB_REQ_FAILED_TC_0_REG	0x202C
#define DSAF_SBM_LNK_INPORT_CNT_0_REG		0x2030
#define DSAF_SBM_LNK_DROP_CNT_0_REG		0x2034
#define DSAF_SBM_INF_OUTPORT_CNT_0_REG		0x2038
#define DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG	0x203C
#define DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG	0x2040
#define DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG	0x2044
#define DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG	0x2048
#define DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG	0x204C
#define DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG	0x2050
#define DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG	0x2054
#define DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG	0x2058
#define DSAF_SBM_LNK_REQ_CNT_0_REG		0x205C
#define DSAF_SBM_LNK_RELS_CNT_0_REG		0x2060
#define DSAF_SBM_BP_CFG_3_REG_0_REG		0x2068
#define DSAF_SBM_BP_CFG_4_REG_0_REG		0x206C

#define DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG	0x3000
#define DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG	0x3004
#define DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG	0x3008
#define DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG	0x300C
#define DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG	0x3010
#define DSAF_XOD_ETS_TOKEN_CFG_0_REG		0x3014
#define DSAF_XOD_PFS_CFG_0_0_REG		0x3018
#define DSAF_XOD_PFS_CFG_1_0_REG		0x301C
#define DSAF_XOD_PFS_CFG_2_0_REG		0x3020
#define DSAF_XOD_GNT_L_0_REG			0x3024
#define DSAF_XOD_GNT_H_0_REG			0x3028
#define DSAF_XOD_CONNECT_STATE_0_REG		0x302C
#define DSAF_XOD_RCVPKT_CNT_0_REG		0x3030
#define DSAF_XOD_RCVTC0_CNT_0_REG		0x3034
#define DSAF_XOD_RCVTC1_CNT_0_REG		0x3038
#define DSAF_XOD_RCVTC2_CNT_0_REG		0x303C
#define DSAF_XOD_RCVTC3_CNT_0_REG		0x3040
#define DSAF_XOD_RCVVC0_CNT_0_REG		0x3044
#define DSAF_XOD_RCVVC1_CNT_0_REG		0x3048
#define DSAF_XOD_XGE_RCVIN0_CNT_0_REG		0x304C
#define DSAF_XOD_XGE_RCVIN1_CNT_0_REG		0x3050
#define DSAF_XOD_XGE_RCVIN2_CNT_0_REG		0x3054
#define DSAF_XOD_XGE_RCVIN3_CNT_0_REG		0x3058
#define DSAF_XOD_XGE_RCVIN4_CNT_0_REG		0x305C
#define DSAF_XOD_XGE_RCVIN5_CNT_0_REG		0x3060
#define DSAF_XOD_XGE_RCVIN6_CNT_0_REG		0x3064
#define DSAF_XOD_XGE_RCVIN7_CNT_0_REG		0x3068
#define DSAF_XOD_PPE_RCVIN0_CNT_0_REG		0x306C
#define DSAF_XOD_PPE_RCVIN1_CNT_0_REG		0x3070
#define DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG		0x3074
#define DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG		0x3078
#define DSAF_XOD_FIFO_STATUS_0_REG		0x307C
#define DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG	0x3A00
#define DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET	0x4

#define DSAF_VOQ_ECC_INVERT_EN_0_REG		0x4004
#define DSAF_VOQ_SRAM_PKT_NUM_0_REG		0x4008
#define DSAF_VOQ_IN_PKT_NUM_0_REG		0x400C
#define DSAF_VOQ_OUT_PKT_NUM_0_REG		0x4010
#define DSAF_VOQ_ECC_ERR_ADDR_0_REG		0x4014
#define DSAF_VOQ_BP_STATUS_0_REG		0x4018
#define DSAF_VOQ_SPUP_IDLE_0_REG		0x401C
#define DSAF_VOQ_XGE_XOD_REQ_0_0_REG		0x4024
#define DSAF_VOQ_XGE_XOD_REQ_1_0_REG		0x4028
#define DSAF_VOQ_PPE_XOD_REQ_0_REG		0x402C
#define DSAF_VOQ_ROCEE_XOD_REQ_0_REG		0x4030
#define DSAF_VOQ_BP_ALL_THRD_0_REG		0x4034

#define DSAF_TBL_CTRL_0_REG			0x5000
#define DSAF_TBL_INT_MSK_0_REG			0x5004
#define DSAF_TBL_INT_SRC_0_REG			0x5008
#define DSAF_TBL_INT_STS_0_REG			0x5100
#define DSAF_TBL_TCAM_ADDR_0_REG		0x500C
#define DSAF_TBL_LINE_ADDR_0_REG		0x5010
#define DSAF_TBL_TCAM_HIGH_0_REG		0x5014
#define DSAF_TBL_TCAM_LOW_0_REG			0x5018
#define DSAF_TBL_TCAM_MCAST_CFG_4_0_REG		0x501C
#define DSAF_TBL_TCAM_MCAST_CFG_3_0_REG		0x5020
#define DSAF_TBL_TCAM_MCAST_CFG_2_0_REG		0x5024
#define DSAF_TBL_TCAM_MCAST_CFG_1_0_REG		0x5028
#define DSAF_TBL_TCAM_MCAST_CFG_0_0_REG		0x502C
#define DSAF_TBL_TCAM_UCAST_CFG_0_REG		0x5030
#define DSAF_TBL_LIN_CFG_0_REG			0x5034
#define DSAF_TBL_TCAM_RDATA_HIGH_0_REG		0x5038
#define DSAF_TBL_TCAM_RDATA_LOW_0_REG		0x503C
#define DSAF_TBL_TCAM_RAM_RDATA4_0_REG		0x5040
#define DSAF_TBL_TCAM_RAM_RDATA3_0_REG		0x5044
#define DSAF_TBL_TCAM_RAM_RDATA2_0_REG		0x5048
#define DSAF_TBL_TCAM_RAM_RDATA1_0_REG		0x504C
#define DSAF_TBL_TCAM_RAM_RDATA0_0_REG		0x5050
#define DSAF_TBL_LIN_RDATA_0_REG		0x5054
#define DSAF_TBL_DA0_MIS_INFO1_0_REG		0x5058
#define DSAF_TBL_DA0_MIS_INFO0_0_REG		0x505C
#define DSAF_TBL_SA_MIS_INFO2_0_REG		0x5104
#define DSAF_TBL_SA_MIS_INFO1_0_REG		0x5098
#define DSAF_TBL_SA_MIS_INFO0_0_REG		0x509C
#define DSAF_TBL_PUL_0_REG			0x50A0
#define DSAF_TBL_OLD_RSLT_0_REG			0x50A4
#define DSAF_TBL_OLD_SCAN_VAL_0_REG		0x50A8
#define DSAF_TBL_DFX_CTRL_0_REG			0x50AC
#define DSAF_TBL_DFX_STAT_0_REG			0x50B0
#define DSAF_TBL_DFX_STAT_2_0_REG		0x5108
#define DSAF_TBL_LKUP_NUM_I_0_REG		0x50C0