/*
* Copyright (c) 2014-2015 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/cdev.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <asm/cacheflush.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/spinlock.h>
#include "hns_dsaf_main.h"
#include "hns_dsaf_ppe.h"
#include "hns_dsaf_rcb.h"
#define RCB_COMMON_REG_OFFSET 0x80000
#define TX_RING 0
#define RX_RING 1
#define RCB_RESET_WAIT_TIMES 30
#define RCB_RESET_TRY_TIMES 10
/* Because default mtu is 1500, rcb buffer size is set to 2048 enough */
#define RCB_DEFAULT_BUFFER_SIZE 2048
/**
*hns_rcb_wait_fbd_clean - clean fbd
*@qs: ring struct pointer array
*@qnum: num of array
*@flag: tx or rx flag
*/
void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag)
{
int i, wait_cnt;
u32 fbd_num;
for (wait_cnt = i = 0; i < q_num; wait_cnt++) {
usleep_range(200, 300);
fbd_num = 0;
if (flag & RCB_INT_FLAG_TX)
fbd_num += dsaf_read_dev(qs[i],
RCB_RING_TX_RING_FBDNUM_REG);
if (flag & RCB_INT_FLAG_RX)
fbd_num += dsaf_read_dev(qs[i],
RCB_RING_RX_RING_FBDNUM_REG);
if (!fbd_num)
i++;
if (wait_cnt >= 10000)
break;
}
if (i < q_num)
dev_err(qs[i]->handle->owner_dev,
"queue(%d) wait fbd(%d) clean fail!!\n", i, fbd_num);
}
/**
*hns_rcb_reset_ring_hw - ring reset
*@q: ring struct pointer
*/
void hns_rcb_reset_ring_hw(struct hnae_queue *q)
{
u32 wait_cnt;
u32 try_cnt = 0;
u32 could_ret;
u32 tx_fbd_num;
while (try_cnt++ < RCB_RESET_TRY_TIMES) {
usleep_range(100, 200);
tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG);
if (tx_fbd_num)
continue;
dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0);
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
msleep(20);
could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
wait_cnt = 0;
while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) {
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
msleep(20);
could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
wait_cnt++;
}
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
if (could_ret)
break;
}
if (try_cnt >= RCB_RESET_TRY_TIMES)
dev_err(q->dev->dev, "port%d reset ring fail\n",
hns_ae_get_vf_cb(q->handle)->port_index);
}
/**
*hns_rcb_int_ctrl_hw - rcb irq enable control
*@q: hnae queue struct pointer
*@flag:ring flag tx or rx
*@mask:mask
*/
void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
{
u32 int_mask_en = !!mask;
if (flag & RCB_INT_FLAG_TX) {
dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG,
int_mask_en);
}
if (flag & RCB_INT_FLAG_RX) {
dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG,
int_mask_en);
}
}
void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag)
{
if (flag & RCB_INT_FLAG_TX) {
dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1);
dsaf_write_dev(