1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
|
/*
* Copyright (c) 2014-2015 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __HNS_DSAF_MAIN_H
#define __HNS_DSAF_MAIN_H
#include "hnae.h"
#include "hns_dsaf_reg.h"
#include "hns_dsaf_mac.h"
struct hns_mac_cb;
#define DSAF_DRV_NAME "hns_dsaf"
#define DSAF_MOD_VERSION "v1.0"
#define DSAF_DEVICE_NAME "dsaf"
#define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000
#define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/
#define DSAF_MAX_CHIP_NUM 2 /*max 2 chips */
#define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22
#define HNS_DSAF_MAX_DESC_CNT 1024
#define HNS_DSAF_MIN_DESC_CNT 16
#define DSAF_INVALID_ENTRY_IDX 0xffff
#define DSAF_CFG_READ_CNT 30
#define DSAF_DUMP_REGS_NUM 504
#define DSAF_STATIC_NUM 28
#define DSAF_V2_STATIC_NUM 44
#define DSAF_PRIO_NR 8
#define DSAF_REG_PER_ZONE 3
#define DSAF_ROCE_CREDIT_CHN 8
#define DSAF_ROCE_CHAN_MODE 3
enum dsaf_roce_port_mode {
DSAF_ROCE_6PORT_MODE,
DSAF_ROCE_4PORT_MODE,
DSAF_ROCE_2PORT_MODE,
DSAF_ROCE_CHAN_MODE_NUM,
};
enum dsaf_roce_port_num {
DSAF_ROCE_PORT_0,
DSAF_ROCE_PORT_1,
DSAF_ROCE_PORT_2,
DSAF_ROCE_PORT_3,
DSAF_ROCE_PORT_4,
DSAF_ROCE_PORT_5,
};
enum dsaf_roce_qos_sl {
DSAF_ROCE_SL_0,
DSAF_ROCE_SL_1,
DSAF_ROCE_SL_2,
DSAF_ROCE_SL_3,
};
#define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
#define HNS_DSAF_IS_DEBUG(dev) (dev->dsaf_mode == DSAF_MODE_DISABLE_SP)
enum hal_dsaf_mode {
HRD_DSAF_NO_DSAF_MODE = 0x0,
HRD_DSAF_MODE = 0x1,
};
enum hal_dsaf_tc_mode {
HRD_DSAF_4TC_MODE = 0X0,
HRD_DSAF_8TC_MODE = 0X1,
};
struct dsaf_vm_def_vlan {
u32 vm_def_vlan_id;
u32 vm_def_vlan_cfi;
u32 vm_def_vlan_pri;
};
struct dsaf_tbl_tcam_data {
u32 tbl_tcam_data_high;
u32 tbl_tcam_data_low;
};
#define DSAF_PORT_MSK_NUM \
((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1)
struct dsaf_tbl_tcam_mcast_cfg {
u8 tbl_mcast_old_en;
u8 tbl_mcast_item_vld;
u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
};
struct dsaf_tbl_tcam_ucast_cfg {
u32 tbl_ucast_old_en;
u32 tbl_ucast_item_vld;
u32 tbl_ucast_mac_discard;
u32 tbl_ucast_dvc;
u32 tbl_ucast_out_port;
};
struct dsaf_tbl_line_cfg {
u32 tbl_line_mac_discard;
u32 tbl_line_dvc;
u32 tbl_line_out_port;
};
enum dsaf_port_rate_mode {
DSAF_PORT_RATE_1000 = 0,
DSAF_PORT_RATE_2500,
DSAF_PORT_RATE_10000
};
enum dsaf_stp_port_type {
DSAF_STP_PORT_TYPE_DISCARD = 0,
DSAF_STP_PORT_TYPE_BLOCK = 1,
DSAF_STP_PORT_TYPE_LISTEN = 2,
DSAF_STP_PORT_TYPE_LEARN = 3,
DSAF_STP_PORT_TYPE_FORWARD = 4
};
enum dsaf_sw_port_type {
DSAF_SW_PORT_TYPE_NON_VLAN = 0,
DSAF_SW_PORT_TYPE_ACCESS = 1,
DSAF_SW_PORT_TYPE_TRUNK = 2,
};
#define DSAF_SUB_BASE_SIZE (0x10000)
/* dsaf mode define */
enum dsaf_mode {
DSAF_MODE_INVALID = 0, /**< Invalid dsaf mode */
DSAF_MODE_ENABLE_FIX, /**< en DSAF-mode, fixed to queue*/
DSAF_MODE_ENABLE_0VM, /**< en DSAF-mode, support 0 VM */
DSAF_MODE_ENABLE_8VM, /**< en DSAF-mode, support 8 VM */
DSAF_MODE_ENABLE_16VM, /**< en DSAF-mode, support 16 VM */
DSAF_MODE_ENABLE_32VM, /**< en DSAF-mode, support 32 VM */
DSAF_MODE_ENABLE_128VM, /**< en DSAF-mode, support 128 VM */
DSAF_MODE_ENABLE, /**< before is enable DSAF mode*/
DSAF_MODE_DISABLE_SP, /* <non-dsaf, single port mode */
DSAF_MODE_DISABLE_FIX, /**< non-dasf, fixed to queue*/
DSAF_MODE_DISABLE_2PORT_8VM, /**< non-dasf, 2port 8VM */
DSAF_MODE_DISABLE_2PORT_16VM, /**< non-dasf, 2port 16VM */
DSAF_MODE_DISABLE_2PORT_64VM, /**< non-dasf, 2port 64VM */
DSAF_MODE_DISABLE_6PORT_0VM, /**< non-dasf, 6port 0VM */
DSAF_MODE_DISABLE_6PORT_2VM, /**< non-dasf, 6port 2VM */
DSAF_MODE_DISABLE_6PORT_4VM, /**< non-dasf, 6port 4VM */
DSAF_MODE_DISABLE_6PORT_16VM, /**< non-dasf, 6port 16VM */
DSAF_MODE_MAX /**< the last one, use as the num */
};
#define DSAF_DEST_PORT_NUM 256 /* DSAF max port num */
#define DSAF_WORD_BIT_CNT 32 /* the num bit of word */
/*mac entry, mc or uc entry*/
struct dsaf_drv_mac_single_dest_entry {
/* mac addr, match the entry*/
u8 addr[ETH_ALEN];
u16 in_vlan_id; /* value of VlanId */
/* the vld input port num, dsaf-mode fix 0, */
/* non-dasf is the entry whitch port vld*/
u8 in_port_num;
u8 port_num; /*output port num*/
u8 rsv[6];
};
/*only mc entry*/
struct dsaf_drv_mac_multi_dest_entry {
/* mac addr, match the entry*/
u8 addr[ETH_ALEN];
u16 in_vlan_id;
/* this mac addr output port,*/
/* bit0-bit5 means Port0-Port5(1bit is vld)**/
u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];
/* the vld input port num, dsaf-mode fix 0,*/
/* non-dasf is the entry whitch port vld*/
u8 in_port_num;
u8 rsv[7];
};
struct dsaf_hw_stats {
u64 pad_drop;
u64 man_pkts;
u64 rx_pkts;
u64 rx_pkt_id;
u64 rx_pause_frame;
u64 release_buf_num;
u64 sbm_drop;
u64 crc_false;
u64 bp_drop;
u64 rslt_drop;
u64 local_addr_false;
u64 vlan_drop;
u64 stp_drop;
u64 rx_pfc[DSAF_PRIO_NR];
u64 tx_pfc[DSAF_PRIO_NR];
u64 tx_pkts;
};
struct hnae_vf_cb {
u8 port_index;
struct hns_mac_cb *mac_cb;
struct dsaf_device *dsaf_dev;
struct hnae_handle ae_handle; /* must be the last number */
};
struct dsaf_int_xge_src {
u32 xid_xge_ecc_err_int_src;
u32 xid_xge_fsm_timout_int_src;
u32 sbm_xge_lnk_fsm_timout_int_src;
u32 sbm_xge_lnk_ecc_2bit_int_src;
u32 sbm_xge_mib_req_failed_int_src;
u32 sbm_xge_mib_req_fsm_timout_int_src;
u32 sbm_xge_mib_rels_fsm_timout_int_src;
u32 sbm_xge_sram_ecc_2bit_int_src;
u32 sbm_xge_mib_buf_sum_err_int_src;
u32 sbm_xge_mib_req_extra_int_src;
u32 sbm_xge_mib_rels_extra_int_src;
u32 voq_xge_start_to_over_0_int_src;
u32 voq_xge_start_to_over_1_int_src;
u32 voq_xge_ecc_err_int_src;
};
struct dsaf_int_ppe_src {
u32 xid_ppe_fsm_timout_int_src;
u32 sbm_ppe_lnk_fsm_timout_int_src;
u32 sbm_ppe_lnk_ecc_2bit_int_src;
u32 sbm_ppe_mib_req_failed_int_src;
u32 sbm_ppe_mib_req_fsm_timout_int_src;
u32 sbm_ppe_mib_rels_fsm_timout_int_src;
u32 sbm_ppe_sram_ecc_2bit_int_src;
u32 sbm_ppe_mib_buf_sum_err_int_src;
u32 sbm_ppe_mib_req_extra_int_src;
u32 sbm_ppe_mib_rels_extra_int_src;
u32 voq_ppe_start_to_over_0_int_src;
u32 voq_ppe_ecc_err_int_src;
u32 xod_ppe_fifo_rd_empty_int_src;
u32 xod_ppe_fifo_wr_full_int_src;
};
struct dsaf_int_rocee_src {
u32 xid_rocee_fsm_timout_int_src;
u32 sbm_rocee_lnk_fsm_timout_int_src;
u32 sbm_rocee_lnk_ecc_2bit_int_src;
u32 sbm_rocee_mib_req_failed_int_src;
u32 sbm_rocee_mib_req_fsm_timout_int_src;
u32 sbm_rocee_mib_rels_fsm_timout_int_src;
u32 sbm_rocee_sram_ecc_2bit_int_src;
u32 sbm_rocee_mib_buf_sum_err_int_src;
u32 sbm_rocee_mib_req_extra_int_src;
u32 sbm_rocee_mib_rels_extra_int_src;
u32 voq_rocee_start_to_over_0_int_src;
u32 voq_rocee_ecc_err_int_src;
};
struct dsaf_int_tbl_src {
u32 tbl_da0_mis_src;
u32 tbl_da1_mis_src;
u32 tbl_da2_mis_src;
u32 tbl_da3_mis_src;
u32 tbl_da4_mis_src;
u32 tbl_da5_mis_src;
u32 tbl_da6_mis_src;
u32 tbl_da7_mis_src;
u32 tbl_sa_mis_src;
u32 tbl_old_sech_end_src;
u32 lram_ecc_err1_src;
u32 lram_ecc_err2_src;
u32 tram_ecc_err1_src;
u32 tram_ecc_err2_src;
u32 tbl_ucast_bcast_xge0_src;
u32 tbl_ucast_bcast_xge1_src;
u32 tbl_ucast_bcast_xge2_src;
u32 tbl_ucast_bcast_xge3_src;
u32 tbl_ucast_bcast_xge4_src;
u32 tbl_ucast_bcast_xge5_src;
u32 tbl_ucast_bcast_ppe_src;
u32 tbl_ucast_bcast_rocee_src;
};
struct dsaf_int_stat {
struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN];
struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN];
struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN];
struct dsaf_int_tbl_src dsaf_int_tbl_stat[1];
};
struct dsaf_misc_op {
void (*cpld_set_led)(struct hns_mac_cb *mac_cb, int link_status,
u16 speed, int data);
void (*cpld_reset_led)(struct hns_mac_cb *mac_cb);
int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb,
enum hnae_led_state status);
/* reset series function, it will be reset if the dereset is 0 */
void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset);
void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
void (*xge_core_srst)(struct dsaf_device *dsaf_dev, u32 port,
bool dereset);
void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset);
void (*hns_dsaf_srst_chns)(struct dsaf_device *dsaf_dev, u32 msk,
bool dereset);
void (*hns_dsaf_roce_srst)(struct dsaf_device *dsaf_dev, bool dereset);
phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb);
int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt);
int (*cfg_serdes_loopback)(struct hns_mac_cb *mac_cb, bool en);
};
/* Dsaf device struct define ,and mac -> dsaf */
struct dsaf_device
|