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/* Copyright (c) 2014 Linaro Ltd.
* Copyright (c) 2014 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/ktime.h>
#include <linux/of_address.h>
#include <linux/phy.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#define PPE_CFG_RX_ADDR 0x100
#define PPE_CFG_POOL_GRP 0x300
#define PPE_CFG_RX_BUF_SIZE 0x400
#define PPE_CFG_RX_FIFO_SIZE 0x500
#define PPE_CURR_BUF_CNT 0xa200
#define GE_DUPLEX_TYPE 0x08
#define GE_MAX_FRM_SIZE_REG 0x3c
#define GE_PORT_MODE 0x40
#define GE_PORT_EN 0x44
#define GE_SHORT_RUNTS_THR_REG 0x50
#define GE_TX_LOCAL_PAGE_REG 0x5c
#define GE_TRANSMIT_CONTROL_REG 0x60
#define GE_CF_CRC_STRIP_REG 0x1b0
#define GE_MODE_CHANGE_REG 0x1b4
#define GE_RECV_CONTROL_REG 0x1e0
#define GE_STATION_MAC_ADDRESS 0x210
#define PPE_CFG_CPU_ADD_ADDR 0x580
#define PPE_CFG_MAX_FRAME_LEN_REG 0x408
#define PPE_CFG_BUS_CTRL_REG 0x424
#define PPE_CFG_RX_CTRL_REG 0x428
#define PPE_CFG_RX_PKT_MODE_REG 0x438
#define PPE_CFG_QOS_VMID_GEN 0x500
#define PPE_CFG_RX_PKT_INT 0x538
#define PPE_INTEN 0x600
#define PPE_INTSTS 0x608
#define PPE_RINT 0x604
#define PPE_CFG_STS_MODE 0x700
#define PPE_HIS_RX_PKT_CNT 0x804
/* REG_INTERRUPT */
#define RCV_INT BIT(10)
#define RCV_NOBUF BIT(8)
#define RCV_DROP BIT(7)
#define TX_DROP BIT(6)
#define DEF_INT_ERR (RCV_NOBUF | RCV_DROP | TX_DROP)
#define DEF_INT_MASK (RCV_INT | DEF_INT_ERR)
/* TX descriptor config */
#define TX_FREE_MEM BIT(0)
#define TX_READ_ALLOC_L3 BIT(1)
#define TX_FINISH_CACHE_INV BIT(2)
#define TX_CLEAR_WB BIT(4)
#define TX_L3_CHECKSUM BIT(5)
#define TX_LOOP_BACK BIT(11)
/* RX error */
#define RX_PKT_DROP BIT(0)
#define RX_L2_ERR BIT(1)
#define RX_PKT_ERR (RX_PKT_DROP | RX_L2_ERR)
#define SGMII_SPEED_1000 0x08
#define SGMII_SPEED_100 0x07
#define SGMII_SPEED_10 0x06
#define MII_SPEED_100 0x01
#define MII_SPEED_10 0x00
#define GE_DUPLEX_FULL BIT(0)
#define GE_DUPLEX_HALF 0x00
#define GE_MODE_CHANGE_EN BIT(0)
#define GE_TX_AUTO_NEG BIT(5)
#define GE_TX_ADD_CRC BIT(6)
#define GE_TX_SHORT_PAD_THROUGH BIT(7)
#define GE_RX_STRIP_CRC BIT(0)
#define GE_RX_STRIP_PAD BIT(3)
#define GE_RX_PAD_EN BIT(4)
#define GE_AUTO_NEG_CTL BIT(0)
#define GE_RX_INT_THRESHOLD BIT(6)
#define GE_RX_TIMEOUT 0x04
#define GE_RX_PORT_EN BIT(1)
#define GE_TX_PORT_EN BIT(2)
#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(12)
#define PPE_CFG_RX_PKT_ALIGN BIT(18)
#define PPE_CFG_QOS_VMID_MODE BIT(14)
#define PPE_CFG_QOS_VMID_GRP_SHIFT 8
#define PPE_CFG_RX_FIFO_FSFU BIT(11)
#define PPE_CFG_RX_DEPTH_SHIFT 16
#define PPE_CFG_RX_START_SHIFT 0
#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11
#define PPE_CFG_BUS_LOCAL_REL BIT(14)
#define PPE_CFG_BUS_BIG_ENDIEN BIT(0)
#define RX_DESC_NUM 128
#define TX_DESC_NUM 256
#define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM-1))
#define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
#define GMAC_PPE_RX_PKT_MAX_LEN 379
#define GMAC_MAX_PKT_LEN 1516
#define GMAC_MIN_PKT_LEN 31
#define RX_BUF_SIZE 1600
#define RESET_TIMEOUT 1000
#define TX_TIMEOUT (6 * HZ)
#define DRV_NAME "hip04-ether"
#define DRV_VERSION "v1.0"
#define HIP04_MAX_TX_COALESCE_USECS 200
#define HIP04_MIN_TX_COALESCE_USECS 100
#define HIP04_MAX_TX_COALESCE_FRAMES 200
#define HIP04_MIN_TX_COALESCE_FRAMES 100
struct tx_desc {
u32 send_addr;
u32 send_size;
u32 next_addr;
u32 cfg;
u32 wb_addr;
} __aligned(64);
struct rx_desc {
u16 reserved_16;
u16 pkt_len;
u32 reserve1[3];
u32 pkt_err;
u32 reserve2[4];
};
struct hip04_priv {
void __iomem *base;
int phy_mode;
int chan;
unsigned int port;
unsigned int speed;
unsigned int duplex;
unsigned int reg_inten;
struct napi_struct napi;
struct net_device *ndev;
struct tx_desc *tx_desc;
dma_addr_t tx_desc_dma;
struct sk_buff *tx_skb[TX_DESC_NUM];
dma_addr_t tx_phys[TX_DESC_NUM];
unsigned int tx_head;
int tx_coalesce_frames;
int tx_coalesce_usecs;
struct hrtimer tx_coalesce_timer;
unsigned char *rx_buf[RX_DESC_NUM];
dma_addr_t rx_phys[RX_DESC_NUM];
unsigned int rx_head;
unsigned int rx_buf_size;
struct device_node *phy_node;
struct phy_device *phy;
struct regmap *map;
struct work_struct tx_timeout_task;
/* written only by tx cleanup */
unsigned int tx_tail ____cacheline_aligned_in_smp;
};
static inline unsigned int tx_count(unsigned int head, unsigned int tail)
{
return (head - tail) % (TX_DESC_NUM - 1);
}
static void hip04_config_port(struct net_device *ndev, u32 speed, u32 duplex)
{
struct hip04_priv *priv = netdev_priv(ndev);
u32 val;
priv->speed = speed;
priv->duplex = duplex;
switch (priv->phy_mode) {
case PHY_INTERFACE_MODE_SGMII:
if (speed == SPEED_1000)
val = SGMII_SPEED_1000;
else if (speed == SPEED_100)
val = SGMII_SPEED_100;
else
val = SGMII_SPEED_10;
break;
case PHY_INTERFACE_MODE_MII:
if (speed == SPEED_100)
val = MII_SPEED_100;
else
val = MII_SPEED_10;
break;
default:
netdev_warn(ndev, "not supported mode\n");
val = MII_SPEED_10;
break;
}
writel_relaxed(val, priv->base + GE_PORT_MODE);
val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF;
writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
val = GE_MODE_CHANGE_EN;
writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
}
static void hip04_reset_ppe(struct hip04_priv *priv)
{
u32 val, tmp, timeout = 0;
do {
regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);
regmap_read(priv->map, priv->port * 4
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